- 专利标题: ENABLING SECURE STATE-CLEAN DURING CONFIGURATION OF PARTIAL RECONFIGURATION BITSTREAMS ON FPGA
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申请号: US18300622申请日: 2023-04-14
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公开(公告)号: US20230297727A1公开(公告)日: 2023-09-21
- 发明人: Alpa Trivedi , Scott Weber , Steffen Schulz , Patrick Koeberl
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 主分类号: G06F21/85
- IPC分类号: G06F21/85 ; G06F30/398 ; G06N3/04 ; H04L9/08 ; G06F9/30 ; G06F9/50 ; G06F15/177 ; G06F15/78 ; H04L9/40 ; G06F11/07 ; G06F30/331 ; G06F9/38 ; G06F11/30
摘要:
An apparatus to facilitate enabling secure state-clean during configuration of partial reconfiguration bitstreams on accelerator devices is disclosed. The apparatus includes a security engine to perform, as part of a PR configuration sequence for a new partial reconfiguration (PR) persona corresponding to a PR bitstream, a first clear operation to clear previously-set persona configuration bits in the region; perform, as part of the PR configuration sequence subsequent to the first clear operation, a set operation to set new persona configuration bits in the region; and perform, as part of the PR configuration sequence, a second clear operation to clear memory blocks of the region that became unfrozen subsequent to the set operation.
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