- 专利标题: MANAGING SUB-BLOCK ERASE OPERATIONS IN A MEMORY SUB-SYSTEM
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申请号: US18224179申请日: 2023-07-20
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公开(公告)号: US20230360709A1公开(公告)日: 2023-11-09
- 发明人: Kalyan Chakravarthy Kavalipurapu , Tomoko Ogura Iwasaki , Erwin E. Yu , Hong-Yan Chen , Yunfei Xu
- 申请人: Micron Technology, Inc.
- 申请人地址: US ID Boise
- 专利权人: Micron Technology, Inc.
- 当前专利权人: Micron Technology, Inc.
- 当前专利权人地址: US ID Boise
- 主分类号: G11C16/16
- IPC分类号: G11C16/16 ; G06F3/06 ; G11C16/04 ; G11C16/08
摘要:
A processing device in a memory system connects a first data block of the memory device to a second data block of the memory device to generate a combined data block comprising a first plurality of sub-blocks of the first data block and a second plurality of sub-blocks of the second data block, wherein the connecting includes: for each wordline of a first plurality of wordlines of the first data block, creating a wordline connection short between the respective wordline of the first data block and a corresponding wordline of a second plurality of wordlines of the second data block, wherein the first plurality of wordlines and the second plurality of wordlines comprise data wordlines; and driving a first data wordline of the first data block and a second wordline of the second data block using a single string driver of the memory device.
公开/授权文献
- US12068037B2 Managing sub-block erase operations in a memory sub-system 公开/授权日:2024-08-20
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