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    RATING-BASED MAPPING OF DATA TO MEMORY
    1.
    发明申请
    RATING-BASED MAPPING OF DATA TO MEMORY 有权

    公开(公告)号：US20240370198A1

    公开(公告)日：2024-11-07

    申请号：US18666290

    申请日：2024-05-16

    Applicant: Micron Technology, Inc.

    Inventor： Carla L. Christensen ,  Gangotree Chakma ,  Yingqi Zheng ,  Yunfei Xu ,  Bhumika Chhabra

    IPC: G06F3/06

    Abstract: Methods, systems, and devices for rating-based mapping of data to memory are described. A memory system may determine a first rating for a set of data selected for writing to a memory system. The memory system may select a target page of a block in the memory system for writing the set of data based at least in part on a second rating for the target page. The memory system may write the set of data to the target page based at least in part on the first rating for the set of data corresponding to the second rating for the target page.

    MANAGING SUB-BLOCK ERASE OPERATIONS IN A MEMORY SUB-SYSTEM
    3.
    发明申请
    MANAGING SUB-BLOCK ERASE OPERATIONS IN A MEMORY SUB-SYSTEM 有权

    公开(公告)号：US20220277795A1

    公开(公告)日：2022-09-01

    申请号：US17745852

    申请日：2022-05-16

    Applicant: Micron Technology, Inc.

    Inventor： Kalyan Chakravarthy Kavalipurapu ,  Tomoko Ogura Iwasaki ,  Erwin E. Yu ,  Hong-Yan Chen ,  Yunfei Xu

    IPC: G11C16/16 ,  G06F3/06 ,  G11C16/04 ,  G11C16/08

    Abstract: A processing device in a memory system receives an erase request to erase data stored at a data block of a memory device, the erase request identifying a selected sub-block of a plurality of sub-blocks of the data block for erase, each of the plurality of sub-blocks comprising select gate devices (SGDs) and data storage devices. For each sub-block of the plurality of sub-blocks not selected for erase, the processing device applies an input voltage at a bitline of the respective sub-block and applies a plurality of gate voltages to a plurality of wordlines of the respective sub-block, the plurality of wordlines are coupled to the SGDs and to the data storage devices, each voltage of the plurality of voltages applied to a successive wordline of the plurality of wordlines is less than a previous voltage applied to a previous wordline.

    Managing sub-block erase operations in a memory sub-system
    4.
    发明授权
    Managing sub-block erase operations in a memory sub-system 有权

    公开(公告)号：US11335412B2

    公开(公告)日：2022-05-17

    申请号：US16991836

    申请日：2020-08-12

    Applicant: Micron Technology, Inc.

    Inventor： Kalyan Chakravarthy Kavalipurapu ,  Tomoko Ogura Iwasaki ,  Erwin E. Yu ,  Hong-Yan Chen ,  Yunfei Xu

    IPC: G11C16/16 ,  G06F3/06 ,  G11C16/04 ,  G11C16/08

    Abstract: A processing device in a memory system receives an erase request to erase data stored at a data block of a memory device, the erase request identifying a selected sub-block of a plurality of sub-blocks of the data block for erase, each of the plurality of sub-blocks comprising select gate devices (SGDs) and data storage devices. For each sub-block of the plurality of sub-blocks not selected for erase, the processing device applies an input voltage at a bitline of the respective sub-block and applies a plurality of gate voltages to a plurality of wordlines of the respective sub-block, the plurality of wordlines are coupled to the SGDs and to the data storage devices, each voltage of the plurality of voltages applied to a successive wordline of the plurality of wordlines is less than a previous voltage applied to a previous wordline by an amount equal to a step down interval.

    Rating-based mapping of data to memory
    5.
    发明授权
    Rating-based mapping of data to memory 有权

    公开(公告)号：US12299319B2

    公开(公告)日：2025-05-13

    申请号：US18666290

    申请日：2024-05-16

    Applicant: Micron Technology, Inc.

    Inventor： Carla L. Christensen ,  Gangotree Chakma ,  Yingqi Zheng ,  Yunfei Xu ,  Bhumika Chhabra

    IPC: G06F3/06

    Abstract: Methods, systems, and devices for rating-based mapping of data to memory are described. A memory system may determine a first rating for a set of data selected for writing to a memory system. The memory system may select a target page of a block in the memory system for writing the set of data based at least in part on a second rating for the target page. The memory system may write the set of data to the target page based at least in part on the first rating for the set of data corresponding to the second rating for the target page.

    MANAGING SUB-BLOCK ERASE OPERATIONS IN A MEMORY SUB-SYSTEM
    10.
    发明申请
    MANAGING SUB-BLOCK ERASE OPERATIONS IN A MEMORY SUB-SYSTEM 有权

    公开(公告)号：US20210202009A1

    公开(公告)日：2021-07-01

    申请号：US16991836

    申请日：2020-08-12

    Applicant: Micron Technology, Inc.

    Inventor： Kalyan Chakravarthy Kavalipurapu ,  Tomoko Ogura Iwasaki ,  Erwin E. Yu ,  Hong-Yan Chen ,  Yunfei Xu

    IPC: G11C16/16 ,  G06F3/06 ,  G11C16/08 ,  G11C16/04

    Abstract: A processing device in a memory system receives an erase request to erase data stored at a data block of a memory device, the erase request identifying a selected sub-block of a plurality of sub-blocks of the data block for erase, each of the plurality of sub-blocks comprising select gate devices (SGDs) and data storage devices. For each sub-block of the plurality of sub-blocks not selected for erase, the processing device applies an input voltage at a bitline of the respective sub-block and applies a plurality of gate voltages to a plurality of wordlines of the respective sub-block, the plurality of wordlines are coupled to the SGDs and to the data storage devices, each voltage of the plurality of voltages applied to a successive wordline of the plurality of wordlines is less than a previous voltage applied to a previous wordline by an amount equal to a step down interval.

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