- 专利标题: BOTTOM IMPLANT AND AIRGAP ISOLATION FOR NANOSHEET SEMICONDUCTOR DEVICES
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申请号: US17480482申请日: 2021-09-21
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公开(公告)号: US20230089482A1公开(公告)日: 2023-03-23
- 发明人: Yan Zhang , Johannes M. van Meer , Naushad K. Variam
- 申请人: Applied Materials, Inc.
- 申请人地址: US CA Santa Clara
- 专利权人: Applied Materials, Inc.
- 当前专利权人: Applied Materials, Inc.
- 当前专利权人地址: US CA Santa Clara
- 主分类号: H01L21/764
- IPC分类号: H01L21/764 ; H01L27/092 ; H01L21/8238
摘要:
A semiconductor manufacturing process and semiconductor device having an airgap to isolate bottom implant portions of a substrate from upper source and drain device structure to reduce bottom current leakage and parasitic capacitance with an improved scalability on n-to-p spacing scaling. The disclosed device can be implanted to fabricate nanosheet FET and other such semiconductor device. The airgap is formed by etching into the substrate, below a trench in a vertical and horizontal direction. The trench is then filled with dielectric and upper device structure formed on either side of the dielectric filler trench.
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