- 专利标题: SCALABLE RUNTIME VALIDATION FOR ON-DEVICE DESIGN RULE CHECKS
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申请号: US18070655申请日: 2022-11-29
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公开(公告)号: US20230089869A1公开(公告)日: 2023-03-23
- 发明人: Furkan Turan , Patrick Koeberl , Alpa Trivedi , Steffen Schulz , Scott Weber
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 主分类号: G06F21/85
- IPC分类号: G06F21/85 ; G06F30/398 ; G06N3/04 ; H04L9/08 ; G06F9/30 ; G06F9/50 ; G06F15/177 ; G06F15/78 ; H04L9/40 ; G06F11/07 ; G06F30/331 ; G06F9/38 ; G06F11/30
摘要:
An apparatus to facilitate scalable runtime validation for on-device design rule checks is disclosed. The apparatus includes a memory to store a contention set, multiplexers, and a validator. In one implementation, the validator is to: receive design rule information for the multiplexers, the design rule information referencing the contention set, wherein the contention set identifies a determined harmful bitstream configuration for each multiplexer instance of the multiplexers, and wherein the contention set comprises a mapping of contents of a user bitstream to configuration bits of the multiplexers; receive, at the validator of the apparatus, the user bitstream for programming the multiplexers of the apparatus; analyze, at the validator using the design rule information, the user bitstream against the contention set at a programming time of the apparatus; and provide an error indication responsive to identifying a match between the user bitstream and the contention set.