Invention Application
- Patent Title: APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS FOR STRUCTURED-SPARSE TILE MATRIX FMA
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Application No.: US17485363Application Date: 2021-09-25
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Publication No.: US20230102279A1Publication Date: 2023-03-30
- Inventor: Menachem ADELMAN , Robert VALENTINE , Dan BAUM , Amit GRADSTEIN , Simon RUBANOVICH , Regev SHEMY , Zeev SPERBER , Alexander HEINECKE , Christopher HUGHES , Evangelos GEORGANAS , Mark CHARNEY , Arik NARKIS , Rinat RAPPOPORT , Barukh ZIV , Yaroslav POLLAK , Nilesh JAIN , Yash AKHAURI , Brinda GANESH , Rajesh POORNACHANDRAN , Guy BOUDOUKH
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F17/16

Abstract:
Systems, methods, and apparatuses relating sparsity based FMA. In some examples, an instance of a single FMA instruction has one or more fields for an opcode, one or more fields to identify a source/destination matrix operand, one or more fields to identify a first plurality of source matrix operands, one or more fields to identify a second plurality of matrix operands, wherein the opcode is to indicate that execution circuitry is to select a proper subset of data elements from the first plurality of source matrix operands based on sparsity controls from a first matrix operand of the second plurality of matrix operands and perform a FMA.
Information query