Invention Application
- Patent Title: LAMINATED VARISTOR
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Application No.: US17768271Application Date: 2020-09-24
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Publication No.: US20230134880A1Publication Date: 2023-05-04
- Inventor: SAYAKA MATSUMOTO , KEN YANAI , MASASHI TAKAMURA , MASAYA HATTORI , TOMOMITSU MURAISHI
- Applicant: Panasonic Intellectual property Management Co., Ltd.
- Applicant Address: JP Osaka
- Assignee: Panasonic Intellectual property Management Co., Ltd.
- Current Assignee: Panasonic Intellectual property Management Co., Ltd.
- Current Assignee Address: JP Osaka
- Priority: JP2019-204344 20191112,JP2020-019475 20200207
- International Application: PCT/JP2020/036012 WO 20200924
- Main IPC: H01C1/14
- IPC: H01C1/14 ; H01C7/18 ; H01C7/10

Abstract:
It is aimed to provide a laminated varistor capable of reducing stray capacitance to occur between an internal electrode and an external electrode, and also capable of reducing a variation in the stray capacitance due to a variation in the external electrode. A laminated varistor of the present disclosure has external electrodes on first end surface, second end surface, and first side surface of sintered body. No external electrode is provided on second side surface opposite to first side surface. Varistor regions in which internal electrodes overlap each other in a laminating direction are provided at positions closer to second side surface than to first side surface.
Public/Granted literature
- US12106877B2 Chip resistor for reducing stray capacitance Public/Granted day:2024-10-01
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