Invention Publication
- Patent Title: REMOTE SCALABLE MACHINE CHECK ARCHITECTURE
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Application No.: US17854788Application Date: 2022-06-30
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Publication No.: US20240004750A1Publication Date: 2024-01-04
- Inventor: Vilas K. Sridharan , Magiting Talisayon , Srikanth Masanam , Dean A. Liberty
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F11/07
- IPC: G06F11/07

Abstract:
An apparatus and method for supporting communication during error handling in a computing system. A computing system includes a first partition and a second partition, each capable of performing error management based on a respective machine check architecture (MCA). The first partition includes a host processor that executes an exception handler for managing reported errors. A message converter unit of the second partition assists in generating messages based on detected errors in the second partition. The message converter unit receives requests from hardware components of the second partition for handling errors and translates MCA addresses between the first partition and the second partition. To support the message converter unit, during an earlier bootup operation, the second partition communicates the hardware topology of the second partition to the host processor, and the host processor sends address translation information.
Public/Granted literature
- US12111719B2 Remote scalable machine check architecture Public/Granted day:2024-10-08
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