Invention Publication
- Patent Title: SIDE-CHANNEL RESISTANT BULK AES ENCRYPTION
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Application No.: US17810019Application Date: 2022-06-30
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Publication No.: US20240007267A1Publication Date: 2024-01-04
- Inventor: Raghavan Kumar , Sanu K. Mathew
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H04L9/06
- IPC: H04L9/06

Abstract:
In one example an apparatus comprises a first input node to receive a first plaintext input, a second input node to receive a second plaintext input, a third input node to receive a random mask and an advanced encryption standard (AES) circuitry configurable to operate in one of a first mode in which the random mask is added to the first plaintext input during one or more computations to convert the first plaintext input to a first ciphertext output, or a second mode in which the first plaintext input is converted to a first ciphertext output and the second plaintext input is converted to a second ciphertext output without using the random mask. Other examples may be described.
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