Analog-to-digital converters (ADCs) of an integrated circuit includes a first set of ADCs and second set of ADCs in which the ADCs of the first set are of a different type than the ADCs of the second set. On-chip testing of the ADCs includes calibrating an N-bit differential digital-to-analog converter (DAC) and storing a pair of calibration codes for each of 2N possible DAC input codes for the DAC in an on-chip memory. The first set of ADCs is tested using the pairs of calibration codes stored in the on-chip memory and a full N-bit resolution of the DAC. Subsequently, the second set of ADCs is tested using pairs of calibration codes corresponding to a reduced M-bit resolution of the DAC, in which M is less than N. During the testing of the second set of ADCs, a portion of the calibration codes stored in the on-chip memory is overwritten.