公开(公告)号：US20240339170A1

公开(公告)日：2024-10-10

申请号：US18748620

申请日：2024-06-20

申请人： Micron Technology, Inc.

发明人： Scott E. SCHAEFER

IPC分类号： G11C29/46 ,  G11C29/42 ,  G11C29/44

CPC分类号： G11C29/46 ,  G11C29/42 ,  G11C29/4401

摘要： Implementations described herein relate to interrupting a memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify, based on the one or more bits, that the memory built-in self-test is to be interrupted while the memory built-in self-test is being performed using a test mode. The memory device may be permitted to interrupt the memory built-in self-test while the memory built-in self-test is being performed using the test mode but may not be permitted to interrupt the memory built-in self-test while the memory built-in self-test is being performed using a repair mode. The memory device may interrupt the memory built-in self-test while the memory built-in self-test is being performed using the test mode.

公开(公告)号：US20240203518A1

公开(公告)日：2024-06-20

申请号：US18084704

申请日：2022-12-20

申请人： NXP B.V.

发明人： Soenke Ostertun

IPC分类号： G11C29/46 ,  G11C7/24 ,  G11C29/40

CPC分类号： G11C29/46 ,  G11C7/24 ,  G11C29/40 ,  G11C2029/1204

摘要： In a non-volatile memory (NVM) system of a memory device, a memory controller connected to memory cell arrays of the NVM system is configured to perform the steps of selecting a memory cell to test, energizing a test circuit connected to the memory cell under a first biasing condition, reading a measurement of an electrical property of the memory cell, and determining, based on the measurement, whether the memory cell is formed or unformed. In embodiments, the system and method include protecting the test circuit from attack by validating the results of the testing. The memory controller is further configured to energize the test circuit under a second biasing condition that produces a known test result whether the memory cell is formed or unformed; if the result of the second test is not the expected result, the memory controller determines that the testing circuit is malfunctioning or under attack.

公开(公告)号：US12009050B2

公开(公告)日：2024-06-11

申请号：US17875960

申请日：2022-07-28

申请人： Micron Technology, Inc.

发明人： Yang Lu ,  Kang-Yong Kim

IPC分类号： G11C7/00 ,  G11C7/10 ,  G11C29/46

CPC分类号： G11C7/1063 ,  G11C7/1066 ,  G11C7/1096 ,  G11C29/46

摘要： Methods, systems, and devices for selective access for grouped memory dies are described. A memory device may be configured with a select die access protocol for a group of memory dies that share a same channel. The protocol may be enabled by one or more commands from the host device, which may be communicated to each of the memory dies of the group via the channel. The command(s) may indicate a first set of one or more memory dies of the group for which a set of commands may be enabled and may also indicate a second set of one or more memory dies of the group for which at least a subset of the set of commands is disabled. When the select die access mode is enabled, the disabled memory dies may be restricted from performing the subset of commands received via the channel.

公开(公告)号：US20240177790A1

公开(公告)日：2024-05-30

申请号：US18058740

申请日：2022-11-24

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Wei-Chun CHEN

IPC分类号： G11C29/12 ,  G11C29/46

CPC分类号： G11C29/1201 ,  G11C29/12015 ,  G11C29/46

摘要： A testing method includes the following steps of: accessing a memory chip to put the memory chip into a write leveling mode; inputting a strobe signal into the memory chip under the write leveling mode; adjusting signal edges of the strobe signal to sample a clock state of a clock signal in the memory chip under the write leveling mode; generating a data signal according to the strobe signal under the write leveling mode; and determining types of the memory chip according to the data signal under the write leveling mode.

公开(公告)号：US11984180B2

公开(公告)日：2024-05-14

申请号：US17807314

申请日：2022-06-16

申请人： Micron Technology, Inc.

发明人： Scott E. Schaefer

IPC分类号： G11C29/00 ,  G11C29/10 ,  G11C29/42 ,  G11C29/44 ,  G11C29/46

CPC分类号： G11C29/42 ,  G11C29/10 ,  G11C29/4401 ,  G11C29/46

摘要： Implementations described herein relate to enabling or disabling on-die error-correcting code for a memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify, based on the one or more bits, whether the memory built-in self-test is to be performed with on-die error-correcting code (ECC) disabled or with on-die ECC enabled. The memory device may perform the memory built-in self-test, and selectively test for one or more single-bit errors, based on identifying whether the memory built-in self-test is to be performed with the on-die ECC disabled or with the on-die ECC enabled.

公开(公告)号：US20240145023A1

公开(公告)日：2024-05-02

申请号：US18341192

申请日：2023-06-26

申请人： Samsung Electronics Co., Ltd.

发明人： Chang-Wook SEO ,  SangYong Yoon ,  Keeho Jung

IPC分类号： G11C29/46 ,  G11C29/12

CPC分类号： G11C29/46 ,  G11C29/1201

摘要： A memory device includes a test mode detector circuit that determines whether the memory device has entered a test mode based on at least one test mode entry signal received through at least one pin of a plurality of pins and generates a test mode detection signal, and a test pad connection circuit that electrically couples a first pin of the plurality of pins to a dedicated test pad of the test mode such that a signal applied to the first pin is transmitted to the dedicated test pad based on the test mode detection signal.

公开(公告)号：US11967392B2

公开(公告)日：2024-04-23

申请号：US17841673

申请日：2022-06-16

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Chenggong Zhou

IPC分类号： G11C29/46 ,  G11C7/08 ,  G11C29/12 ,  G11C29/44

CPC分类号： G11C29/46 ,  G11C7/08 ,  G11C29/12005 ,  G11C29/4401 ,  G11C2029/1202 ,  G11C2029/1204

摘要： There are provided a method for testing failure of a memory, an apparatus for testing failure of a memory, a computer-readable storage medium, and an electronic device. The method for testing failure of a memory includes: writing preset storage data into a storage array of the memory (S310); raising a bit line voltage, and controlling a part of word lines of the storage array to enter a test mode (S320); exiting the test mode after waiting for preset time (S330); turning off sense amplifiers corresponding to a preset part of bit lines, and reading data from a remaining part of the bit lines (S340); comparing the data read from the remaining part of the bit lines with the preset storage data to obtain a comparison result (S350); and determining a failure state of the memory according to the comparison result (S360).

公开(公告)号：US20240120014A1

公开(公告)日：2024-04-11

申请号：US18100969

申请日：2023-01-24

申请人： SK hynix Inc.

发明人： Suk Hwan CHOI

IPC分类号： G11C29/12 ,  G11C29/18 ,  G11C29/46

CPC分类号： G11C29/12005 ,  G11C29/18 ,  G11C29/46 ,  G11C2029/1202 ,  G11C2029/1802

摘要： The present technology may include: a current mirror configured to apply a test current that is generated by a test voltage to a selected word line, among a plurality of word lines, and to generate a copy current by copying the test current; a comparison circuit configured to compare at least one reference current with the copy current to generate a comparison result signal; and a test control circuit configured to perform a first noise control mode that charges unselected word lines, among the plurality of word lines, with electric charges, in response to a test mode signal and floats the unselected word lines.

公开(公告)号：US11923042B2

公开(公告)日：2024-03-05

申请号：US17581445

申请日：2022-01-21

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sangwoo Kim ,  Younghoon Son ,  Seongheon Yu ,  Joungyeal Kim ,  Chulung Kim

IPC分类号： G11C7/22 ,  G11C7/10 ,  G11C29/12 ,  G11C29/46

CPC分类号： G11C7/222 ,  G11C7/1069 ,  G11C7/1096 ,  G11C29/12015 ,  G11C29/46

摘要： An apparatus includes a host and a memory device connected to the host through a bus. The bus is used to communicate a data clock controlling data write timing during a write operation executed by the memory device and a read clock controlling data read timing during a read operation executed by the memory device. The memory device performs first duty cycle monitoring that monitors a duty cycle of the data clock, generates a first result, and provides a timing-adjusted data clock, performs second duty cycle monitoring that monitors a duty cycle of the read clock, generates a second result, and provides a timing-adjusted read clock, calculates an offset of the read clock based on the timing-adjusted data clock, the result and the second result, and corrects a duty error of the read clock using a read clock offset code derived from the offset of the read clock.

公开(公告)号：US11915775B2

公开(公告)日：2024-02-27

申请号：US17449297

申请日：2021-09-29

申请人： MICRON TECHNOLOGY, INC.

发明人： Jack Riley ,  Scott Smith ,  Christian Mohr ,  Gary Howe ,  Joshua Alzheimer ,  Yoshinori Fujiwara ,  Sujeet Ayyapureddi ,  Randall Rooney

IPC分类号： G11C29/44 ,  G11C29/00 ,  G11C29/18 ,  G11C29/46 ,  G11C29/12

CPC分类号： G11C29/4401 ,  G11C29/18 ,  G11C29/46 ,  G11C29/76 ,  G11C29/787 ,  G11C2029/1202

摘要： Embodiments of the disclosure are drawn to apparatuses and methods for bad row mode. The memory may prevent proper access operations (e.g., read operations) from being performed on a selected bad row of the memory as part of a bad row mode. For example, the memory may store a bad row address and when an access address matches the bad row address, may suppress one or more signals, change data read from the address, or combinations thereof. The bad row mode may be used to provide a positive control for post package repair (PPR) operations on the memory. A controller may enter the memory into bad row mode and then test the memory to determine if the selected bad row can be located and repaired via PPR.