Invention Publication
- Patent Title: MASKED-VECTOR-COMPARISON INSTRUCTION
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Application No.: US18247595Application Date: 2021-08-17
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Publication No.: US20240028337A1Publication Date: 2024-01-25
- Inventor: Jacob EAPEN , Matthias Lothar BOETTCHER , Balaji VENU , François Christopher Jacques BOTMAN
- Applicant: ARM LIMITED
- Applicant Address: GB Cambridge, Cambridgeshire
- Assignee: ARM LIMITED
- Current Assignee: ARM LIMITED
- Current Assignee Address: GB Cambridge, Cambridgeshire
- Priority: GB 15816.8 2020.10.06
- International Application: PCT/GB2021/052130 2021.08.17
- Date entered country: 2023-03-31
- Main IPC: G06F9/30
- IPC: G06F9/30

Abstract:
A masked-vector-comparison instruction specifies a source vector operand comprising a plurality of source data elements, a mask value, and a comparison target operand. In response to the masked-vector-comparison instruction, an instruction decoder 10 controls processing circuitry 16 to: for each active source data element of the source vector operand, determine whether the active source data element satisfies a comparison condition, based on a masked comparison between one or more compared bits of the active source data element and one or more compared bits of the comparison target operand, the mask value specifying a pattern of compared bits and non-compared bits within the comparison target operand and the active source data element; and generate a result value indicative of which of the source data elements of the source vector operand, if any, is an active source data element satisfying the comparison condition. This instruction is useful for variable length decoding operations.
Public/Granted literature
- US12277420B2 Masked-vector-comparison instruction Public/Granted day:2025-04-15
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