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公开(公告)号：US20170031682A1
公开(公告)日：2017-02-02
申请号：US14814582
申请日：2015-07-31
Applicant: ARM LIMITED
Inventor： Jacob EAPEN , Mbou EYOLE , Simon HOSIE
IPC: G06F9/30
CPC classification number: G06F9/30036 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032
Abstract: An apparatus comprises processing circuitry to generate a result vector including at least one N-bit data element in response to an element size increasing instruction identifying at least a first input vector including M-bit data elements, where N>M. First and second forms of the element size increasing instruction are provided for generating the result vector using first and second subsets of data elements of the first input vector respectively. Positions of the first and second subsets of data elements in the first input vector are interleaved.
Abstract translation: 一种装置包括处理电路，以响应于识别包括M位数据元素的至少第一输入向量的元素大小增加指令来生成包括至少一个N位数据元素的结果向量，其中N> M。 提供元素大小增加指令的第一和第二形式，用于分别使用第一输入向量的数据元素的第一和第二子集来生成结果向量。 数据元素的第一和第二子集在第一输入向量中的位置被交织。
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公开(公告)号：US20190303155A1
公开(公告)日：2019-10-03
申请号：US16468108
申请日：2017-11-10
Applicant: ARM LIMITED
Inventor： Jacob EAPEN , Grigorios MAGKLIS , Mbou EYOLE
Abstract: A replicate elements instruction defining a plurality of variable length segments in a result vector controls processing circuitry (80) to generate a result vector in which, in each respective segment, a repeating value is repeated throughout that segment of the result vector, the repeating value comprising a data value or element index of a selected data element of a source vector. This instructions is useful for accelerating processing of data structures smaller than the vector length.
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公开(公告)号：US20200097289A1
公开(公告)日：2020-03-26
申请号：US16468098
申请日：2017-11-10
Applicant: ARM LIMITED
Inventor： Jacob EAPEN , Grigorios MAGKLIS , Mbou EYOLE
IPC: G06F9/30
Abstract: In response to a replicate partition instruction specifying partition information defining positions of a plurality of variable size partitions within a result vector, an instruction decoder (20) controls the processing circuitry (80) to generate a result vector in which each partition having more than one data element comprises data values or element indices of a sequence of data elements of a source vector starting or ending at a selected data element position. This instruction can be useful for accelerating processing of data structures smaller than the vector length.
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公开(公告)号：US20240354105A1
公开(公告)日：2024-10-24
申请号：US18762800
申请日：2024-07-03
Applicant: ARM LIMITED
Inventor： Nigel John STEPHENS , Jacob EAPEN , Mbou EYOLE
IPC: G06F9/30
CPC classification number: G06F9/30032 , G06F9/30018 , G06F9/30036
Abstract: An apparatus and a method are provided for performing a splice operation, the apparatus having a set of vector registers and one or more control registers. Processing circuitry is arranged to execute a sequence of instructions including a splice instruction that identifies at least a first vector register and at least one control register. The first vector register stores a first vector of data elements having a vector length, and the at least one control register stores control data identifying, independently of the vector length, one or more data elements occupying sequential data element positions within the first vector of data elements. The processing circuitry is responsive to execution of the splice instruction to extract from the first vector each data element identified by the control data in the at least one control register, and to output the extracted data elements within a result vector of data elements that also contains data elements from a second vector. Since the control data in the at least one control register identifies the data elements to be extracted without reference to the vector length, this provides a great deal of flexibility as to how the data elements to be extracted may be selected within the first vector.
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Patent Agency Ranking
公开(公告)号：US20220100673A1
公开(公告)日：2022-03-31
申请号：US17310368
申请日：2020-01-29
Applicant: ARM LIMITED
Inventor： Simon John CRASKE , Jacob EAPEN
Abstract: There is provided an apparatus comprising input circuitry that receives requests comprising input addresses in an input domain. Output circuitry provides output addresses. The output addresses comprise secure physical addresses to secure storage circuitry and non-secure physical addresses to non-secure storage circuitry. Lookup circuitry stores a plurality of mappings comprising at least one mapping between the input addresses and the secure physical addresses, and at least one mapping between the input addresses and the non-secure physical addresses.
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公开(公告)号：US20180210733A1
公开(公告)日：2018-07-26
申请号：US15745478
申请日：2016-06-15
Applicant: ARM LIMITED
Inventor： Nigel John STEPHENS , Jacob EAPEN , Mbou EYOLE
IPC: G06F9/30
CPC classification number: G06F9/30192 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30043
Abstract: An apparatus and a method are provided for performing a splice operation, the apparatus having a set of vector registers and one or more control registers. Processing circuitry is arranged to execute a sequence of instructions including a splice instruction that identifies at least a first vector register and at least one control register. The first vector register stores a first vector of data elements having a vector length, and the at least one control register stores control data identifying one or more data elements occupying sequential data element positions within the first vector of data elements. The processing circuitry is responsive to execution of the splice instruction to extract from the first vector each data element identified by the control data in the at least one control register, and to output the extracted data elements within sequential data element positions of the result vector starting from a first end of the result vector, and data elements from a second vector are output to the remaining result vector data element positions not occupied by the extracted data elements from the first vector.
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公开(公告)号：US20240028337A1
公开(公告)日：2024-01-25
申请号：US18247595
申请日：2021-08-17
Applicant: ARM LIMITED
Inventor： Jacob EAPEN , Matthias Lothar BOETTCHER , Balaji VENU , François Christopher Jacques BOTMAN
IPC: G06F9/30
CPC classification number: G06F9/30145 , G06F9/30021 , G06F9/30038
Abstract: A masked-vector-comparison instruction specifies a source vector operand comprising a plurality of source data elements, a mask value, and a comparison target operand. In response to the masked-vector-comparison instruction, an instruction decoder 10 controls processing circuitry 16 to: for each active source data element of the source vector operand, determine whether the active source data element satisfies a comparison condition, based on a masked comparison between one or more compared bits of the active source data element and one or more compared bits of the comparison target operand, the mask value specifying a pattern of compared bits and non-compared bits within the comparison target operand and the active source data element; and generate a result value indicative of which of the source data elements of the source vector operand, if any, is an active source data element satisfying the comparison condition. This instruction is useful for variable length decoding operations.
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公开(公告)号：US20200233742A1
公开(公告)日：2020-07-23
申请号：US16251503
申请日：2019-01-18
Applicant: Arm Limited
Abstract: An apparatus comprising data processing circuitry for processing data in one of a plurality of operating states, an instruction decoder for decoding instructions and error checking circuitry for performing error checking operations. In response to a touch instruction being decoded by the instruction decoder, error checking operation is performed on selected architectural state. The architectural state is architecturally inaccessible to the operating state. As a result of the touch instruction, the architectural state remains unchanged, at least when no error is detected.
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9.发明申请公开(公告)号：US20190114172A1
公开(公告)日：2019-04-18
申请号：US16090357
申请日：2017-04-06
Applicant: ARM Limited
Inventor： Mbou EYOLE , Jacob EAPEN , Alejandro MARTINEZ VICENTE
Abstract: An apparatus and method are provided for managing address collisions when performing vector operations. The apparatus has a register store for storing vector operands, each vector operand comprising a plurality of elements, and execution circuitry for executing instructions in order to perform operations specified by the instructions. The execution circuitry has access circuitry for performing memory access operations in order to move the vector operands between the register store and memory, and processing circuitry for performing data processing operations using the vector operands. The execution circuitry may be arranged to iteratively execute a vector loop, where during each iteration the execution circuitry executes a sequence of instructions to implement the vector loop. The sequence includes a check instruction identifying a plurality of memory addresses, and the execution circuitry is responsive to execution of the check instruction to determine whether an address hazard condition exists amongst the plurality of memory addresses. N For each iteration of the vector loop, the execution circuitry is responsive to execution of the check instruction determining an absence of the hazard address condition, to employ a default level of vectorisation when executing the sequence of instructions to implement the vector loop. In contrast, in the presence of the address hazard condition, the execution circuitry employs a reduced level of vectorisation when executing the sequence of instructions to implement the vector loop. Such an approach has been found to provide a low latency mechanism for dynamically adjusting the level of vectorisation employed during each iteration of the vector loop, enabling code to be vectorised whilst still enabling efficient performance in the presence of address hazard conditions.
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