- 专利标题： COMBINED FUNCTION IC CELL LAYOUT METHOD AND SYSTEM
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申请号： US18482172申请日： 2023-10-06
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公开(公告)号： US20240030921A1公开(公告)日： 2024-01-25
- 发明人: Ying HUANG , Changlin HUANG , Jing DING , Qingchao MENG
- 申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. , TSMC NANJING COMPANY, LIMITED
- 申请人地址： TW Hsinchu
- 专利权人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,TSMC NANJING COMPANY, LIMITED
- 当前专利权人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,TSMC NANJING COMPANY, LIMITED
- 当前专利权人地址： TW Hsinchu
- 优先权： CN 2210585532.0 2022.05.27
- 主分类号： H03K19/0185
- IPC分类号： H03K19/0185 ; G06F30/392
摘要：
A method of generating an integrated circuit (IC) layout diagram includes arranging a first portion of first through fourth pluralities of active regions and a plurality of gate regions of a cell as a functional circuit in a first portion of the cell, arranging a second portion of the first through fourth pluralities of active regions and the plurality of gate regions of the cell as a one of a decoupling capacitor or an antenna diode in a second portion of the cell, and storing an IC layout diagram of the cell in a storage device.
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