-
公开(公告)号：US20240088129A1
公开(公告)日：2024-03-14
申请号：US18519460
申请日：2023-11-27
发明人： Huaixin XIAN , Yang ZHOU , Qingchao MENG
IPC分类号： H01L27/02 , G06F30/392 , H01L21/8238 , H01L23/528 , H01L27/092
CPC分类号： H01L27/0207 , G06F30/392 , H01L21/823871 , H01L23/5286 , H01L27/092 , G06F2119/12
摘要： An integrated circuit (IC) device includes at least one circuit having an input and an output, and an output connector electrically coupled to the output. The circuit further includes a plurality of transistors electrically coupled with each other between the input and the output. The output is in a first metal layer. The output connector includes a first conductive pattern in the first metal layer, and a second conductive pattern in a second metal layer different from the first metal layer. The second conductive pattern electrically couples the output to the first conductive pattern.
-
公开(公告)号：US20230244846A1
公开(公告)日：2023-08-03
申请号：US17669306
申请日：2022-02-10
发明人： Huaixin XIAN , Zhang-Ying YAN , JiBao ZHANG , Qingchao MENG
IPC分类号： G06F30/392 , H01L21/768 , H01L23/522
CPC分类号： G06F30/392 , H01L21/768 , H01L23/5226
摘要： A current-distributing structure in an integrated circuit (IC) includes a substrate; and first and second active regions on the substrate. First and second sets of gate structures correspondingly overlap the first and second active regions. A first conductive structure in a first metallization layer overlaps the first active region and is electrically coupled to the first set of gate structures. A second conductive structure in the first metallization layer overlaps the second active region and is electrically coupled to the second set of gate structures. A third conductive structure in a second metallization layer is electrically coupled to the first and the second conductive structures.
-
公开(公告)号：US20230029848A1
公开(公告)日：2023-02-02
申请号：US17406643
申请日：2021-08-19
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. , TSMC NANJING COMPANY, LIMITED , TSMC CHINA COMPANY, LIMITED
发明人： Liu HAN , Xin Yong WANG , Qingchao MENG , Huaixin XIAN , Jing DING
摘要： A semiconductor device having a cell region, the cell region including a first set of one or more first blocks and a second set of one or more second blocks. Each of the first blocks including a clock gate and each of the second blocks includes a decoupling capacitor. The first set has two or more first blocks and/or the second set has two or more second blocks. The first blocks of the first set are interleaved with the second blocks of the second set.
-
公开(公告)号：US20220405456A1
公开(公告)日：2022-12-22
申请号：US17362305
申请日：2021-06-29
发明人： Huaixin XIAN , Liu HAN , Jing DING , Qingchao MENG
IPC分类号： G06F30/392 , H03K17/687 , H03K3/037
摘要： An integrated circuit includes a clocking transistor, a first enabling transistor, a second enabling transistor, a branch-one transistor, a branch-two transistor, and a clock gating circuit. The first enabling transistor is coupled between the clocking transistor and a first node. The second enabling transistor is coupled between the clocking transistor and a second node. The branch-one transistor is coupled between a first power supply and the first node. The gate terminal of the branch-one transistor is electrically connected to the second node. The branch-two transistor is coupled between the first power supply and the second node. The gate terminal of the branch-two transistor is electrically connected to the first node. The clock gating circuit for generating a gated clock signal receives a latch output signal which is latched to a logic level of either a first node signal or a second node signal.
-
公开(公告)号：US20240030921A1
公开(公告)日：2024-01-25
申请号：US18482172
申请日：2023-10-06
发明人： Ying HUANG , Changlin HUANG , Jing DING , Qingchao MENG
IPC分类号： H03K19/0185 , G06F30/392
CPC分类号： H03K19/018521 , G06F30/392 , G06F2119/06
摘要： A method of generating an integrated circuit (IC) layout diagram includes arranging a first portion of first through fourth pluralities of active regions and a plurality of gate regions of a cell as a functional circuit in a first portion of the cell, arranging a second portion of the first through fourth pluralities of active regions and the plurality of gate regions of the cell as a one of a decoupling capacitor or an antenna diode in a second portion of the cell, and storing an IC layout diagram of the cell in a storage device.
-
公开(公告)号：US20240030920A1
公开(公告)日：2024-01-25
申请号：US18479378
申请日：2023-10-02
发明人： Jing DING , Zhang-Ying YAN , Qingchao MENG , Yi-Ting CHEN
IPC分类号： H03K19/0185 , H03K3/356
CPC分类号： H03K19/018521 , H03K3/356182 , H03K3/356113
摘要： A semiconductor device includes: first and second input circuits in a central region and correspondingly configured to operate in a first voltage domain; first and second single bit level shifters (SBLSs) correspondingly in first and second regions at first and second sides of the central region relative to a first direction and electrically coupled correspondingly to the first and second input circuits, and correspondingly configured to operate in a second voltage domain; and a control circuit configured to toggle each of the first and second SBLSs between a normal state and a standby state when a control signal is received from the control circuit.
-
公开(公告)号：US20230402446A1
公开(公告)日：2023-12-14
申请号：US18447857
申请日：2023-08-10
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. , TSMC NANJING COMPANY, LIMITED , TSMC CHINA COMPANY, LIMITED
发明人： Liu HAN , Xin Yong WANG , Qingchao MENG , Huaixin XIAN , Jing DING
CPC分类号： H01L27/0207 , H03K19/0016 , H01L27/0629
摘要： A semiconductor device having a cell region, the cell region including a first set of one or more first blocks and a second set of one or more second blocks. Each of the first blocks including a clock gate and each of the second blocks includes a decoupling capacitor. The first set has two or more first blocks and/or the second set has two or more second blocks. The first blocks of the first set are interleaved with the second blocks of the second set.
-
公开(公告)号：US20220360253A1
公开(公告)日：2022-11-10
申请号：US17815156
申请日：2022-07-26
发明人： Huaixin XIAN , Qingchao MENG , Yang ZHOU , Shang-Chih HSIEH
IPC分类号： H03K3/037 , H03K3/288 , H03K3/356 , H03K3/3562 , H03K3/289
摘要： A method of forming a semiconductor device includes forming active regions, forming S/D regions, forming MD contact structures and forming gate lines resulting in corresponding transistors that define a first time delay circuit having a first input configured to receive a first clock signal and having a first output configured to generate a second clock signal from the first clock signal; and corresponding transistors that define a second time delay circuit having a second input configured to receive the second clock signal and having a second output configured to generate a third clock signal from the first clock signal; forming a first gate via-connector in direct contact with the first gate line atop the first-type active region in the first area; and forming a second gate via-connector in direct contact with the second gate line atop the second-type active region in the second area.
-
公开(公告)号：US20240128956A1
公开(公告)日：2024-04-18
申请号：US18536552
申请日：2023-12-12
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. , TSMC CHINA COMPANY, LIMITED , TSMC NANJING COMPANY, LIMITED
发明人： Jing DING , Zhang-Ying YAN , Qingchao MENG , Lei PAN
IPC分类号： H03K3/037 , G06F30/392 , H03K19/0185
CPC分类号： H03K3/037 , G06F30/392 , H03K19/018521
摘要： An integrated circuit includes an input circuit coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second or a third input signal, and a level shifter circuit coupled to the input circuit and a second voltage supply, and configured to receive a first enable signal, the second or third input signal, and to generate a first signal responsive to the first enable signal, the second or third input signal. The input circuit includes a first set of transistors having a first threshold voltage. The first set of transistors includes a first set of active regions extending in a first direction. The level shifter circuit includes a second set of transistors having a second threshold voltage. The second set of transistors includes a second set of active regions extending in the first direction.
-
公开(公告)号：US20240048135A1
公开(公告)日：2024-02-08
申请号：US18489692
申请日：2023-10-18
发明人： Huaixin XIAN , Liu HAN , Jing DING , Qingchao MENG
IPC分类号： H03K5/135 , G06F30/392 , H03K3/037 , H03K17/687 , G06F1/04
CPC分类号： H03K5/135 , G06F30/392 , H03K3/037 , H03K17/6872 , G06F1/04 , G06F2117/04
摘要： An integrated circuit includes a clocking transistor, a first enabling transistor, a second enabling transistor, a branch-one transistor, and a branch-two transistor. The first enabling transistor is coupled between the clocking transistor and a first node. The second enabling transistor is coupled between the clocking transistor and a second node. The branch-one transistor is coupled between a first power supply and the first node. The gate terminal of the branch-one transistor is connected to the second node. The branch-two transistor is coupled between the first power supply and the second node. The gate terminal of the branch-two transistor is connected to the first node. Each of the clocking transistor, the first enabling transistor, and the second enabling transistor is a first-type transistor of a reduced threshold. Each of the branch-one transistor and the branch-two transistor is a second-type transistor of a default threshold.
-
-
-
-
-
-
-
-
-
搜索结果
28 条记录 (耗时 0.023 秒)
