A multi-core architecture in some examples may have hundreds of “cores”, each core comprising a digital signal processor (DSP) and various functional computing units. A method of implementing a multi-core graph compiler for a system-on-chip (SOC) having a data processing engine (DPE) array is disclosed herein. An Adaptive Intelligence Engine (AIE) compiler is one example of a multi-core graph compiler. An compiler is used to mitigate performance degradation due to memory stalls (collisions) when executing an AIE compiler-accelerated application on an AI Engine. The method disclosed here addresses phase order issues to mitigate the memory collisions.