A semiconductor device includes a first ADC configured to sample an input signal based on a first clock signal, quantize the input signal with a first gain, and output a plurality of first output signals, and a second ADC configured to sample the input signal based on a second clock signal obtained by delaying the first clock signal, quantize the input signal with a second gain, and output a plurality of second output signals. The device includes a gain mismatch estimator configured to calculate first and second values which are averages of absolute values of the first output signals and the second output signals, and calculate first and second gain correction values using the first and second values. A gain mismatch compensator is configured to output a plurality of corrected first output signals and corrected second output signals, according to the first and second gain correction values.