A display panel includes a base substrate, a transistor disposed on the base substrate and including a semiconductor pattern including a source area, a drain area, and an active area, a gate insulating pattern layer disposed on the semiconductor pattern, and a gate electrode disposed on the gate insulating pattern, and connection electrodes disposed on the gate insulating pattern layer and connected to the semiconductor pattern through contact holes, respectively. The gate insulating pattern layer includes a first portion overlapping at least one of the source area and the drain area and a second portion extending from the first portion. A thickness of the first portion is equal to or smaller than about 50% of a thickness of the second portion.