Disclosed is a structure including a field effect transistor (FET). The FET includes, on an insulator layer above a substrate, source/drain regions and a section of a semiconductor layer extending laterally between the source/drain regions. A primary gate structure is made of the insulator layer and a well region in the substrate opposite at least the section of the semiconductor layer extending laterally between the source/drain regions. One or two secondary gate structures are on the semiconductor layer between and near one or both of the source/drain regions, respectively. The FET can further include a patterned conformal dielectric layer, which is on the center of the semiconductor layer between the source/drain regions, and which extends onto the secondary gate structure(s). Also disclosed are methods of operating the structure by biasing the secondary gate structure(s) to adjust the effective gate length of the FET and methods of forming the structure.