Invention Publication
- Patent Title: GLITCH REDUCTION IN PHASE SHIFTERS
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Application No.: US17933230Application Date: 2022-09-19
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Publication No.: US20240097656A1Publication Date: 2024-03-21
- Inventor: Ravindranath D. SHRIVASTAVA , Fleming LAM , Payman SHANJANI
- Applicant: pSemi Corporation
- Applicant Address: US CA San Diego
- Assignee: pSemi Corporation
- Current Assignee: pSemi Corporation
- Current Assignee Address: US CA San Diego
- Main IPC: H03H11/24
- IPC: H03H11/24 ; H03H7/20

Abstract:
Methods and devices to reduce glitches in phase shifters implementing high isolation switches are disclosed. Such glitches occur at the output of the phase shifters when transitioning from one phase shift to another. The disclosed method implements delays in various steps of the phase shifter transitions. Exemplary embodiments implementing single-pole multi-throw are provided and exemplary performance of the disclosed methods are also presented. The described methods are also applicable to multi-step attenuators.
Public/Granted literature
- US12101072B2 Glitch reduction in phase shifters Public/Granted day:2024-09-24
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