An integrated circuit (IC) die includes a first layer with conductive structures formed in a interlayer dielectric (ILD) material, with a portion of the conductive structures at a first surface of the first layer, a self-alignment layer in contact with non-conductive regions at the first surface of the first layer, a second layer with ILD material in contact with the self-alignment layer and the portion of the conductive structures at the first surface of the first layer, and conductive vias through the self-alignment layer and the second layer in contact with the portion of the conductive structures at the first surface of the first layer. The self-alignment layer may include a first material where the self-alignment layer is in contact with the conductive vias and a second material where the self-alignment layer is not in contact with the conductive vias. Other embodiments are disclosed and claimed.