- 专利标题： Array of Memory Cells, Methods Used in Forming an Array of Memory Cells, Methods Used in Forming an Array of Vertical Transistors, Methods Used in Forming an Array of Vertical Transistors, and Methods Used in Forming an Array of Capacitors
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申请号： US18533574申请日： 2023-12-08
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公开(公告)号： US20240107747A1公开(公告)日： 2024-03-28
- 发明人: Antonino Rigano
- 申请人： Micron Technology, Inc.
- 申请人地址： US ID Boise
- 专利权人： Micron Technology, Inc.
- 当前专利权人： Micron Technology, Inc.
- 当前专利权人地址： US ID Boise
- 分案原申请号： US17106832 2020.11.30
- 主分类号： H10B12/00
- IPC分类号： H10B12/00 ; G11C11/22 ; H01L29/78 ; H10B53/30 ; H10B53/40
摘要：
A method used in forming an array of memory cells comprises forming a vertical stack comprising transistor material directly above and directly against a first capacitor electrode material. A mask is used to subtractively etch both the transistor material and thereafter the first capacitor electrode material to form a plurality of pillars that individually comprise the transistor material and the first capacitor electrode material. Capacitors are formed that individually comprise the first capacitor electrode material of individual of the pillars. Vertical transistors are formed above the capacitors that individually comprise the transistor material of the individual pillars. Other aspects and embodiments are disclosed, including structure independent of method.
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