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    SEMICONDUCTOR CHIP
    3.
    发明公开
    SEMICONDUCTOR CHIP 审中-公开

    公开(公告)号：US20240015985A1

    公开(公告)日：2024-01-11

    申请号：US18471316

    申请日：2023-09-21

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Bo-Feng Young ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Chih-Yu Chang ,  Han-Jong Chia

    IPC分类号： H10B53/40 ,  H01L23/522

    CPC分类号： H10B53/40 ,  H01L23/5226

    摘要： A semiconductor chip including a semiconductor substrate, an interconnect structure and a memory cell array is provided. The semiconductor substrate includes a logic circuit. The interconnect structure is disposed on the semiconductor substrate and electrically connected to the logic circuit, and the interconnect structure includes stacked interlayer dielectric layers and interconnect wirings embedded in the stacked interlayer dielectric layers. The memory cell array is embedded in the stacked interlayer dielectric layers. The memory cell array includes driving transistors and memory devices, and the memory devices are electrically connected the driving transistors through the interconnect wirings.

    FERROELECTRIC MEMORY ARCHITECTURE WITH GAP REGION
    4.
    发明公开
    FERROELECTRIC MEMORY ARCHITECTURE WITH GAP REGION 审中-公开

    公开(公告)号：US20230397436A1

    公开(公告)日：2023-12-07

    申请号：US18204077

    申请日：2023-05-31

    申请人： Micron Technology, Inc.

    发明人： Giorgio Servalli ,  Marcello Mariani

    IPC分类号： H10B53/30 ,  H10B53/40

    CPC分类号： H10B53/30 ,  G11C11/2273 ,  H10B53/40

    摘要： Methods, systems, and devices for a ferroelectric memory architecture are described. A memory architecture may include a gap region between memory cells to reduce a capacitance between plates coupled with the memory cells. The gap region may include a fluid, such as air, which may have a relatively low dielectric constant to reduce a capacitance between plates and reduce (e.g., eliminate) undesirable coupling between plates during memory operations. Implementing the gap region between memory cells enables a memory device to increase speed and reduce resource consumption associated with memory operations

    Embedded memory with encapsulation layer adjacent to a memory stack
    5.
    发明授权
    Embedded memory with encapsulation layer adjacent to a memory stack 有权

    公开(公告)号：US11785782B1

    公开(公告)日：2023-10-10

    申请号：US17346094

    申请日：2021-06-11

    申请人： Kepler Computing Inc.

    发明人： Noriyuki Sato ,  Tanay Gosavi ,  Niloy Mukherjee ,  Rajeev Kumar Dokania ,  Amrita Mathuriya ,  Sasikanth Manipatruni

    IPC分类号： H10B53/40

    CPC分类号： H10B53/40

    摘要： A process integration and patterning flow used to pattern a memory array area for an embedded memory without perturbing a fabricating process for logic circuitries. The fabrication process uses a pocket mask (e.g., a hard mask) to decouple the etching process of a memory array area and non-memory area. Such decoupling allows for a simpler fabrication process with little to no impact on the current fabrication process. The fabrication process may use multiple pocket masks to decouple the etching process of the memory array area and the non-memory area. This fabrication process (using multiple pocket masks) allows to avoid exposure of memory material into a second pocket etch chamber. The process of etching memory material is decoupled from the process of etching an encapsulation material. Examples of embedded memory include dynamic random-access memory and ferroelectric random-access memory.