Invention Publication
- Patent Title: METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURES
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Application No.: US18533291Application Date: 2023-12-08
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Publication No.: US20240107754A1Publication Date: 2024-03-28
- Inventor: Michael A. Smith
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: MICRON TECHNOLOGY, INC.
- Current Assignee: MICRON TECHNOLOGY, INC.
- Current Assignee Address: US ID Boise
- The original application number of the division: US17508353 2021.10.22
- Main IPC: H10B41/27
- IPC: H10B41/27 ; H10B41/35 ; H10B41/41 ; H10B43/27 ; H10B43/35 ; H10B43/40

Abstract:
Method of forming an isolation structure might include forming a first conductive region in a first section of a semiconductor material, forming a first trench in a second section of the semiconductor material adjacent a first side of the first section of the semiconductor material and forming a second trench in a third section of the semiconductor material adjacent a second side of the first section of the semiconductor material, extending the first and second trenches to a depth below the first conductive region and removing a portion of the first section of the semiconductor material overlying the first conductive region, forming second and third conductive regions in the semiconductor material below bottoms of the first and second trenches, respectively, and forming a dielectric material overlying the first conductive region and filling the first and second trenches.
Public/Granted literature
- US12274057B2 Methods of forming integrated circuit structures comprising isolation structures with different depths Public/Granted day:2025-04-08
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