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公开(公告)号：US20240365544A1
公开(公告)日：2024-10-31
申请号：US18473896
申请日：2023-09-25
发明人： Quanshan Lv , Jie Yuan , YaLi Song
摘要： Examples of the present application provide a three-dimensional memory and manufacturing method thereof, and a memory system. The three-dimensional memory comprises: a stack structure comprising alternating stacked gate layers and dielectric layers; a plurality of channel columns penetrating the stack structure in a first direction and comprising: a barrier layer, a storage layer, a tunneling layer, and a channel layer arranged in sequence; and a plurality of isolation structures located between the dielectric layers and the tunneling layer in a second direction perpendicular to the first direction; wherein the isolation structures penetrating at least a portion of the storage layer in the second direction.
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公开(公告)号：US20240365542A1
公开(公告)日：2024-10-31
申请号：US18764868
申请日：2024-07-05
发明人： Wei-Cheng WU , Li-Feng TENG
IPC分类号： H10B41/42 , H01L21/28 , H01L29/423 , H01L29/66 , H10B41/30 , H10B41/35 , H10B41/44 , H10B41/47 , H10B41/48 , H10B43/30
CPC分类号： H10B41/42 , H01L29/40114 , H01L29/42328 , H01L29/42344 , H01L29/66545 , H10B41/30 , H10B41/35 , H10B41/44 , H10B41/47 , H10B41/48 , H10B43/30
摘要： A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer, and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.
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3.发明公开公开(公告)号：US20240365541A1
公开(公告)日：2024-10-31
申请号：US18765437
申请日：2024-07-08
发明人： Yu-Hsuan LIN , Feng-Min LEE , Po-Hao TSENG
CPC分类号： H10B41/35 , H01L29/40114 , H01L29/66825
摘要： The application discloses an integrated memory device, a manufacturing method and an operation method thereof. The integrated memory cell includes: a first memory cell; and an embedded second memory cell, serially coupled to the first memory cell, wherein the embedded second memory cell is formed on any one of a first side and a second side of the first memory cell.
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公开(公告)号：US12133382B2
公开(公告)日：2024-10-29
申请号：US17678499
申请日：2022-02-23
发明人： Xiang Yin
IPC分类号： H10B41/27 , G11C16/04 , H01L23/522 , H10B41/10 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
CPC分类号： H10B41/27 , G11C16/0483 , H01L23/5226 , H10B41/10 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
摘要： An alternating stack of insulating layers and sacrificial material layers is formed over a substrate, and support pillar structures are formed through the alternating stack. Stepped surfaces are formed by patterning the alternating stack and the support pillar structures. A retro-stepped dielectric material portion is formed over the stepped surfaces. Memory openings and memory opening fill structures are formed through the alternating stack. Electrically conductive layers are formed by replacing at least the sacrificial material layers with at least one electrically conductive material. Contact via structures are formed through the retro-stepped dielectric material portion on the electrically conductive layers. A first support pillar structure is located directly below a first contact via structure.
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公开(公告)号：US20240357822A1
公开(公告)日：2024-10-24
申请号：US18305653
申请日：2023-04-24
发明人： Min Gyu Sung , Julien Frougier , Ruilong Xie , Chanro Park , Juntao Li
IPC分类号： H10B43/35 , H01L23/528 , H01L25/065 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786 , H10B41/27 , H10B41/35 , H10B43/27 , H10B80/00
CPC分类号： H10B43/35 , H01L23/5283 , H01L25/0657 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/775 , H01L29/78696 , H10B41/27 , H10B41/35 , H10B43/27 , H10B80/00
摘要： A memory device including a stack of nanostructures, a first plurality of nanosheets/nanowires from the stack of nanostructures having first source and drain regions at their opposing ends to position first channel regions for a first memory cell, and a second plurality of nanosheets/nanowires from the stack of nanostructures having second source and drain regions at their opposing ends to position second channel regions for a second memory cell. An isolation liner layer is present between the first source and drain regions and the second source and drain regions. The memory device further includes a shared gate all around (GAA) control gate for the first and second memory cell, the shared gate all around (GAA) control gate including tunnel dielectric layer on the first and second channel regions, a trap dielectric layer on the tunnel dielectric layer, and a control conductor on the trap dielectric layer.
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公开(公告)号：US12127406B2
公开(公告)日：2024-10-22
申请号：US17577533
申请日：2022-01-18
发明人： Takaaki Iwai , Takashi Inomata , Takayuki Maekura
IPC分类号： H01L25/18 , H01L23/00 , H01L23/535 , H01L25/00 , H01L25/065 , H10B41/27 , H10B41/35 , H10B43/27 , H10B43/35 , H10B51/20 , H10B51/30 , H10B63/00
CPC分类号： H10B43/27 , H01L23/535 , H01L24/08 , H01L24/80 , H01L25/0657 , H01L25/18 , H01L25/50 , H10B41/27 , H10B41/35 , H10B43/35 , H10B51/20 , H10B51/30 , H10B63/34 , H10B63/845 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2924/1431 , H01L2924/1441 , H01L2924/1444 , H01L2924/14511
摘要： A semiconductor structure includes an alternating stack of insulating layers and composite layers. Each of the composite layers includes a plurality of electrically conductive word line strips laterally extending along a first horizontal direction and a plurality of dielectric isolation strips laterally extending along the first horizontal direction and interlaced with the plurality of electrically conductive word line strips. Rows of memory openings are arranged along the first horizontal direction. Each row of memory openings vertically extends through each insulating layer within the alternating stack and one electrically conductive strip for each of the composite layers. Rows of memory opening fill structures are located within the rows of memory openings. Each of the memory opening fill structures includes a respective vertical stack of memory elements and a respective vertical semiconductor channel.
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公开(公告)号：US12125808B2
公开(公告)日：2024-10-22
申请号：US18206923
申请日：2023-06-07
发明人： Pascal Fornara , Fabrice Marinet
IPC分类号： H01L29/788 , G06F21/75 , G06F21/79 , H01L23/00 , H01L23/522 , H10B41/35 , G06F21/87
CPC分类号： H01L23/573 , G06F21/75 , G06F21/79 , H01L23/5223 , H01L23/576 , H01L29/7883 , H10B41/35 , G06F21/87
摘要： An integrated circuit memory includes a state transistor having a floating gate which stores a respective data value. A device for protecting the data stored in the memory includes a capacitive structure having a first electrically-conducting body coupled to the floating gate of the state transistor, a dielectric body, and a second electrically-conducting body coupled to a ground terminal. The dielectric body is configured, if an aqueous solution is brought into contact with the dielectric body, to electrically couple the floating gate and the ground terminal so as to modify the charge on the floating gate and to lose the corresponding data. Otherwise, the dielectric body is configured to electrically isolate the floating gate and the ground terminal.
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公开(公告)号：US12125538B2
公开(公告)日：2024-10-22
申请号：US17834024
申请日：2022-06-07
发明人： Won-bo Shim , Ji-ho Cho , Yong-seok Kim , Byoung-taek Kim , Sun-gyung Hwang
IPC分类号： G11C16/10 , G11C11/56 , G11C16/04 , G11C16/08 , G11C16/34 , H01L29/788 , G06F3/06 , H10B41/35 , H10B43/27 , H10B43/35
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/3427 , G11C16/3459 , H01L29/7885 , G06F3/0679 , H10B41/35 , H10B43/27 , H10B43/35
摘要： A program method of a nonvolatile memory device that performs a plurality of program loops is provided. At least one of the plurality of program loops includes dividing a channel of a selected cell string into a first side channel and a second side channel during a first interval and a second interval, turning off a string selection transistor of the selected cell string by applying a string select line voltage of a first level during the first interval, and boosting a first voltage of the first side channel and a second voltage of the second side channel, and turning on the string selection transistor by applying the string select line voltage of a second level different from the first level during the second interval, and performing a hot carrier injection (HCI) program operation on a selected memory cell corresponding to the first side channel or the second side channel.
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公开(公告)号：US12108597B2
公开(公告)日：2024-10-01
申请号：US17684975
申请日：2022-03-02
发明人： Teruo Okina , Shinsuke Yada , Ryo Yoshimoto
IPC分类号： H10B41/27 , G11C16/04 , H01L23/00 , H01L23/522 , H01L23/528 , H01L25/065 , H10B41/10 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
CPC分类号： H10B41/27 , G11C16/0483 , H01L23/5226 , H01L23/5283 , H01L24/06 , H01L24/08 , H01L24/80 , H01L25/0657 , H10B41/10 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35 , H01L2224/06181 , H01L2224/08146 , H01L2224/80001 , H01L2225/06541 , H01L2924/1431 , H01L2924/1451
摘要： A semiconductor structure includes a memory die bonded to a logic die. The memory die includes an alternating stack of insulating layers and electrically conductive layers, a semiconductor material layer located on a distal surface of the alternating stack, a dielectric spacer layer located on a distal surface of the semiconductor material layer, memory opening fill structures vertically extending through the alternating stack, through the semiconductor material layer, and at least partly through the dielectric spacer layer, and a source layer located on a distal surface of the dielectric spacer layer and contacting pillar portions of the vertical semiconductor channels that are embedded within the dielectric spacer layer.
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公开(公告)号：US20240324194A1
公开(公告)日：2024-09-26
申请号：US18602778
申请日：2024-03-12
发明人： Dongjin LEE , Junhee LIM , Hakseon KIM , Kangoh YUN , Sohyun LEE
CPC分类号： H10B41/35 , G11C16/0483 , H01L25/0652 , H10B41/10 , H10B41/27 , H10B41/41 , H10B80/00 , H01L2225/06506
摘要： An integrated circuit device includes a substrate including an active region including a central active region, base active regions and extended active regions integrated together and defined by a device isolation film. A drain region is located in the central active region, and source regions are respectively located in the base active regions. The base active regions are spaced apart from each other in different diagonal directions with respect to the central active region in a plan view. The extended active regions each have an L-shape, connect the central active region and the base active regions, and are spaced apart from each other. Gate structures that respectively cross the base active regions and are spaced apart from each other on the substrate. The central active region, the extended active regions, the base active regions, and the gate structures configure pass transistors, and the pass transistors share the drain region.
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