Invention Publication
- Patent Title: TOP GATE RECESSED CHANNEL CMOS THIN FILM TRANSISTOR AND METHODS OF FABRICATION
-
Application No.: US18395192Application Date: 2023-12-22
-
Publication No.: US20240136277A1Publication Date: 2024-04-25
- Inventor: Gilbert Dewey , Ryan Keech , Cory Bomberger , Cheng-Ying Huang , Ashish Agrawal , Willy Rachmady , Anand Murthy
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L21/762 ; H01L21/768 ; H01L27/12

Abstract:
A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.
Information query
IPC分类: