To provide an operation method of a semiconductor device in which a variation in arithmetic operation results is reduced. The semiconductor device includes first and second cell arrays and first to fifth circuits. First, third standard data is written from the fourth circuit to the second cell array, and first standard data is written from the first circuit to the first cell array. Then, second standard data is transmitted from the second circuit to the first cell array, a result of a product-sum operation of the first standard data and the second standard data is input from the first cell array to the third circuit, and fourth standard data corresponding to the result of the product-sum operation is transmitted from the third circuit to the second cell array. A result of a product-sum operation of the third standard data and the fourth standard data is input from the second cell array to the fifth circuit, and an output value corresponding to the result of the product-sum operation is output from the fifth circuit. Correction data corresponding to the difference between the output value and an expected value is retained in an empty cell of the first cell array and correction coefficients of the first and second cell arrays are calculated.