- 专利标题： MEMORY DEVICE ADJUSTING SKEW OF MULTI-PHASE CLOCK SIGNALS, MEMORY CONTROLLER CONTROLLING THE MEMORY DEVICE, AND OPERATING METHOD OF THE MEMORY DEVICE
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申请号： US18326657申请日： 2023-05-31
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公开(公告)号： US20240144991A1公开(公告)日： 2024-05-02
- 发明人: Jaewoo JEONG , Yonghun KIM , Kihan KIM , Changsik YOO
- 申请人： Samsung Electronics Co., Ltd.
- 申请人地址： KR Suwon-si
- 专利权人： Samsung Electronics Co., Ltd.
- 当前专利权人： Samsung Electronics Co., Ltd.
- 当前专利权人地址： KR Suwon-si
- 优先权： KR 20220140509 2022.10.27
- 主分类号： G11C11/4076
- IPC分类号： G11C11/4076 ; G06F1/10 ; G06F1/12
摘要：
A memory device includes a multi-phase clock generator configured to generate first to N-th clock signals having N different phases based on a clock signal from the memory controller, and a monitoring clock signal generator configured to generate a monitoring clock signal having a logic state corresponding to a data pattern in synchronization with edges of the first to N-th clock signals, wherein the monitoring clock signal includes a first monitoring clock signal configured to detect a skew between the first and third clock signals in a first step of a training operation, a second monitoring clock signal configured to detect a skew between the second and fourth clock signals in a second step of the training operation, and a third monitoring clock signal configured to detect a skew between the first and second clock signals in a third step of the training operation.
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