公开(公告)号：US20240144991A1

公开(公告)日：2024-05-02

申请号：US18326657

申请日：2023-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaewoo JEONG ,  Yonghun KIM ,  Kihan KIM ,  Changsik YOO

IPC: G11C11/4076 ,  G06F1/10 ,  G06F1/12

CPC classification number: G11C11/4076 ,  G06F1/10 ,  G06F1/12

Abstract: A memory device includes a multi-phase clock generator configured to generate first to N-th clock signals having N different phases based on a clock signal from the memory controller, and a monitoring clock signal generator configured to generate a monitoring clock signal having a logic state corresponding to a data pattern in synchronization with edges of the first to N-th clock signals, wherein the monitoring clock signal includes a first monitoring clock signal configured to detect a skew between the first and third clock signals in a first step of a training operation, a second monitoring clock signal configured to detect a skew between the second and fourth clock signals in a second step of the training operation, and a third monitoring clock signal configured to detect a skew between the first and second clock signals in a third step of the training operation.