A pixel circuit and a display panel including the same are disclosed. The display panel includes: an individual switch element configured to supply a pixel driving voltage to a first sub-pixel in response to a gate signal; and a shared switch element configured to supply the pixel driving voltage to second and third sub-pixels in response to the gate signal. Each of the individual switch element and the shared switch element is a transistor having a channel width. The channel width of the shared switch element is larger than the channel width of the individual switch element.