Invention Publication
- Patent Title: Differential To Single-Ended Summation Circuit With Improved Common-Mode Rejection Ratio
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Application No.: US17990682Application Date: 2022-11-19
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Publication No.: US20240171144A1Publication Date: 2024-05-23
- Inventor: Ravikumar Pattipaka , Prashuk Jain , Vajeed Nimran
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Main IPC: H03F3/45
- IPC: H03F3/45
Abstract:
A differential to single-ended summation circuit includes a first switch which includes a first terminal coupled to a first circuit input and includes a second terminal. The circuit includes a second switch which includes a first terminal coupled to a second circuit input and includes a second terminal. The circuit includes a holding capacitor which includes a first terminal coupled to the second terminal of the first switch and a second terminal coupled to the second terminal of the second switch. The circuit includes a third switch which includes a first terminal coupled to the second terminal of the first switch and a second terminal coupled to a circuit output. The circuit includes a fourth switch including a first terminal coupled to the second terminal of the second switch and a second terminal coupled to a common potential.
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