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11 条记录 (耗时 0.014 秒)

    Differential To Single-Ended Summation Circuit With Improved Common-Mode Rejection Ratio
    1.
    发明公开
    Differential To Single-Ended Summation Circuit With Improved Common-Mode Rejection Ratio 审中-公开

    公开(公告)号：US20240171144A1

    公开(公告)日：2024-05-23

    申请号：US17990682

    申请日：2022-11-19

    申请人： Texas Instruments Incorporated

    发明人： Ravikumar Pattipaka ,  Prashuk Jain ,  Vajeed Nimran

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45928 ,  H03F3/45076 ,  H03F2200/231 ,  H03F2200/294

    摘要： A differential to single-ended summation circuit includes a first switch which includes a first terminal coupled to a first circuit input and includes a second terminal. The circuit includes a second switch which includes a first terminal coupled to a second circuit input and includes a second terminal. The circuit includes a holding capacitor which includes a first terminal coupled to the second terminal of the first switch and a second terminal coupled to the second terminal of the second switch. The circuit includes a third switch which includes a first terminal coupled to the second terminal of the first switch and a second terminal coupled to a circuit output. The circuit includes a fourth switch including a first terminal coupled to the second terminal of the second switch and a second terminal coupled to a common potential.

    Passive beamformer
    3.
    发明授权
    Passive beamformer 有权

    公开(公告)号：US10573292B2

    公开(公告)日：2020-02-25

    申请号：US15782945

    申请日：2017-10-13

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Ravikumar Pattipaka ,  Vajeed Nimran ,  Sandeep Oswal

    IPC分类号： G10K11/34 ,  A61B8/00 ,  G01S15/89 ,  A61B8/08 ,  G01S7/52

    摘要： A passive beamformer for ultrasound imaging. An ultrasound probe includes a plurality of ultrasound transducers and beamforming circuitry. Each of the ultrasound transducers is configured to convert ultrasonic signal into electrical signal. The beamforming circuitry is coupled to the plurality of ultrasound transducers. The beamforming circuitry includes a plurality of passive delay circuits and a passive hold circuit. One of the passive delay circuits is coupled to each of the ultrasound transducers. The passive hold circuit is coupled to the passive delay circuits to store a sum of the charges received from the delay circuits.

    TIME GAIN COMPENSATION CIRCUIT IN AN ULTRASOUND RECEIVER
    4.
    发明申请
    TIME GAIN COMPENSATION CIRCUIT IN AN ULTRASOUND RECEIVER 审中-公开
    超声波接收机中的时间增益补偿电路

    公开(公告)号：US20150280662A1

    公开(公告)日：2015-10-01

    申请号：US14637146

    申请日：2015-03-03

    申请人： Texas Instruments Incorporated

    发明人： Vajeed Nimran ,  Raja Sekhar ,  Sandeep Oswal ,  Shagun Dusad

    IPC分类号： H03F3/45 ,  H03F1/56 ,  A61B8/14

    CPC分类号： H03F1/56 ,  G01S7/52033 ,  H03F3/45475 ,  H03F2203/45134 ,  H03F2203/45151 ,  H03F2203/45528 ,  H03F2203/45591 ,  H03G1/0035 ,  H03G3/3005 ,  H03G3/301

    摘要： The disclosure provides a time gain compensation (TGC) circuit. The TGC circuit includes an impedance network. A differential amplifier is coupled to the impedance network. The differential amplifier includes a first input port, a second input port, a first output port and a second output port. A first feedback resistor is coupled between the first input port and the first output port. A second feedback resistor is coupled between the second input port and the second output port. The impedance network provides a fixed impedance to the differential amplifier when a gain of the TGC circuit is changed from a maximum value to a minimum value.

    摘要翻译： 本公开提供了时间增益补偿（TGC）电路。 TGC电路包括阻抗网络。 差分放大器耦合到阻抗网络。 差分放大器包括第一输入端口，第二输入端口，第一输出端口和第二输出端口。 第一反馈电阻耦合在第一输入端口和第一输出端口之间。 第二反馈电阻耦合在第二输入端口和第二输出端口之间。 当TGC电路的增益从最大值变为最小值时，阻抗网络向差分放大器提供固定阻抗。

    TIME GAIN COMPENSATION CIRCUIT IN AN ULTRASOUND RECEIVER
    6.
    发明申请
    TIME GAIN COMPENSATION CIRCUIT IN AN ULTRASOUND RECEIVER 有权

    公开(公告)号：US20210211102A1

    公开(公告)日：2021-07-08

    申请号：US17210251

    申请日：2021-03-23

    申请人： Texas Instruments Incorporated

    发明人： Vajeed Nimran ,  Raja Sekhar ,  Sandeep Oswal ,  Shagun Dusad

    IPC分类号： H03F1/56 ,  H03F3/45

    摘要： The disclosure provides a time gain compensation (TGC) circuit. The TGC circuit includes an impedance network. A differential amplifier is coupled to the impedance network. The differential amplifier includes a first input port, a second input port, a first output port and a second output port. A first feedback resistor is coupled between the first input port and the first output port. A second feedback resistor is coupled between the second input port and the second output port. The impedance network provides a fixed impedance to the differential amplifier when a gain of the TGC circuit is changed from a maximum value to a minimum value.

    Configurable pulser circuit operable across a range of supply voltages
    7.
    发明授权
    Configurable pulser circuit operable across a range of supply voltages 有权

    公开(公告)号：US10583461B2

    公开(公告)日：2020-03-10

    申请号：US15852018

    申请日：2017-12-22

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Aravind Miriyala ,  Naveen Kumar Ginige ,  Vajeed Nimran ,  Saugata Datta ,  Shabbir Amjhera Wala

    IPC分类号： B06B1/02 ,  H03K17/687 ,  A61B8/00

    摘要： A semiconductor device includes a trim storage and an encoder. The trim storage stores trim values. The encoder determines a magnitude of a supply voltage, determines a magnitude of a handle voltage, determines a source-to-handle voltage of a first transistor, and determines a source-to-handle voltage of a second transistor. Further, the encoder determines a target number of selectable first transistor units comprising the first transistor to select for the first transistor. Based on a trim value from the trim storage, the source-to-handle voltage of the first transistor and the source-to-handle voltage of the second transistor, the encoder determines a target number of selectable second transistor units comprising the second transistor to select for the second transistor. The encoder asserts control signals to select the target number of selectable first transistor units and the target number of selectable second transistor units.

    Time gain compensation circuit in an ultrasound receiver
    9.
    发明授权
    Time gain compensation circuit in an ultrasound receiver 有权

    公开(公告)号：US10985708B2

    公开(公告)日：2021-04-20

    申请号：US15980771

    申请日：2018-05-16

    申请人： Texas Instruments Incorporated

    发明人： Vajeed Nimran ,  Raja Sekhar ,  Sandeep Oswal ,  Shagun Dusad

    IPC分类号： H03F1/56 ,  H03F3/45 ,  H03G1/00 ,  H03G3/30 ,  G01S7/52

    摘要： The disclosure provides a time gain compensation (TGC) circuit. The TGC circuit includes an impedance network. A differential amplifier is coupled to the impedance network. The differential amplifier includes a first input port, a second input port, a first output port and a second output port. A first feedback resistor is coupled between the first input port and the first output port. A second feedback resistor is coupled between the second input port and the second output port. The impedance network provides a fixed impedance to the differential amplifier when a gain of the TGC circuit is changed from a maximum value to a minimum value.