Methods, systems, and devices for chip select wiring for a dual device package are described. A circuit board includes a plurality of layers, the plurality of layers including a first outer layer, a second inner layer, and a third outer layer. The circuit board also includes first and second chip select (CS) signal lines routed through the second inner layer of the circuit board, first and second memory devices coupled with the first outer layer and the third outer layer, respectively, a first via coupling the first CS signal line with a first upper memory die of the first memory device and a second lower memory die of the second memory device, and a second via coupling the second CS signal line with a second upper memory die of the second memory device and a first lower memory die of the first memory device.