公开(公告)号：US11467995B2

公开(公告)日：2022-10-11

申请号：US17108742

申请日：2020-12-01

Applicant: Micron Technology, Inc.

Inventor： William A. Lendvay ,  Scott R. Cyr

IPC: G06F13/38 ,  G06F30/392 ,  G06F13/40

Abstract: Methods, systems, and devices for pin mapping for memory devices are described. An apparatus may include a memory array, a plurality of pins, a selector, and a mapping component. The memory array may include a plurality of data lines coupled with a plurality of memory cells. The mapping component may be configured to map a set of data lines to a first set of pins when the selector reflects a first state and to a second set of pins when the selector reflects a second state. The first and second set of pins may have a same quantity of pins. The second set of pins may include pins that are otherwise unused in the second state. The mapping component may be configured to selectively couple unused pins to a fixed potential.

公开(公告)号：US20210383849A1

公开(公告)日：2021-12-09

申请号：US17244942

申请日：2021-04-29

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave ,  Dirgha Khatri ,  Elancheren Durai ,  Quincy R. Holton ,  Timothy M. Hollis ,  Matthew B. Leslie ,  Baekkyu Choi ,  Boe L. Holbrook ,  Yogesh Sharma ,  Scott R. Cyr

IPC: G11C8/18 ,  G11C8/12 ,  G11C8/06 ,  G11C7/10

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which clock trees can be separately optimized to provide a coarse alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal), and/or in which individual memory devices can be isolated for fine-tuning of device-specific alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal). Moreover, individual memory devices can be isolated for fine-tuning of device-specific equalization of a command/address signal (and/or a chip select signal or other control signal).

公开(公告)号：US20240178149A1

公开(公告)日：2024-05-30

申请号：US18520405

申请日：2023-11-27

Applicant: Micron Technology, Inc.

Inventor： Scott R. Cyr ,  David P. Gooch

IPC: H01L23/538 ,  G11C11/408 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/5386 ,  G11C11/408 ,  H01L23/5383 ,  H01L25/18 ,  H10B80/00 ,  H01L24/32

Abstract: Methods, systems, and devices for chip select wiring for a dual device package are described. A circuit board includes a plurality of layers, the plurality of layers including a first outer layer, a second inner layer, and a third outer layer. The circuit board also includes first and second chip select (CS) signal lines routed through the second inner layer of the circuit board, first and second memory devices coupled with the first outer layer and the third outer layer, respectively, a first via coupling the first CS signal line with a first upper memory die of the first memory device and a second lower memory die of the second memory device, and a second via coupling the second CS signal line with a second upper memory die of the second memory device and a first lower memory die of the first memory device.

公开(公告)号：US09786332B2

公开(公告)日：2017-10-10

申请号：US14624298

申请日：2015-02-17

Applicant: Micron Technology, Inc.

Inventor： Scott R. Cyr

IPC: G06F17/50 ,  G11C5/02 ,  H01L25/00 ,  G11C5/06 ,  G11C8/12 ,  H01L25/065

CPC classification number: G11C5/025 ,  G11C5/066 ,  G11C8/12 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06572

Abstract: Semiconductor device assemblies with semiconductor device packages configured to operate in mirror mode are disclosed herein. In one embodiment a semiconductor device assembly includes a first semiconductor device package attached to a front side of a support substrate, and a second semiconductor device package attached to a back side of the support substrate. The first device package includes a plurality of first package contacts having a first arrangement of corresponding pin assignments, and the second device package includes a plurality of second package contacts and a switch circuit operably coupled to the second package contacts. The switch circuit is configured to receive a switch signal via the support substrate, and to assign the second package contacts to either the first arrangement of corresponding pin assignments or a second arrangement of corresponding pin assignments based on the switch signal.

公开(公告)号：US11948661B2

公开(公告)日：2024-04-02

申请号：US17244942

申请日：2021-04-29

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave ,  Dirgha Khatri ,  Elancheren Durai ,  Quincy R. Holton ,  Timothy M. Hollis ,  Matthew B. Leslie ,  Baekkyu Choi ,  Boe L Holbrook ,  Yogesh Sharma ,  Scott R. Cyr

IPC: G11C8/18 ,  G11C7/10 ,  G11C8/06 ,  G11C8/12

CPC classification number: G11C8/18 ,  G11C7/1096 ,  G11C8/06 ,  G11C8/12

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which clock trees can be separately optimized to provide a coarse alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal), and/or in which individual memory devices can be isolated for fine-tuning of device-specific alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal). Moreover, individual memory devices can be isolated for fine-tuning of device-specific equalization of a command/address signal (and/or a chip select signal or other control signal).

公开(公告)号：US11942404B2

公开(公告)日：2024-03-26

申请号：US17411879

申请日：2021-08-25

Applicant: Micron Technology, Inc.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Scott R. Cyr ,  Stephen F. Moxham ,  Matthew A. Prather ,  Scott Smith

IPC: H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L23/00 ,  H01L23/13

CPC classification number: H01L23/49816 ,  H01L23/49827 ,  H01L25/0657 ,  H01L25/105 ,  H01L23/13 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16235 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2225/06506 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/14361

Abstract: Apparatuses, such as semiconductor device packages, may include, for example, a device substrate including a semiconductor material and bond pads coupled with an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on, and electrically connected to, the package substrate. Each ball of the ball grid array positioned and configured to carry a clock signal or a strobe signal may be located in a central column of the ball grid array.

公开(公告)号：US20220068778A1

公开(公告)日：2022-03-03

申请号：US17411879

申请日：2021-08-25

Applicant: Micron Technology, Inc.

Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Scott R. Cyr ,  Stephen F. Moxham ,  Matthew A. Prather ,  Scott Smith

IPC: H01L23/498 ,  H01L25/065 ,  H01L25/10

Abstract: Apparatuses, such as semiconductor device packages, may include, for example, a device substrate including a semiconductor material and bond pads coupled with an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on, and electrically connected to, the package substrate. Each ball of the ball grid array positioned and configured to carry a clock signal or a strobe signal may be located in a central column of the ball grid array.

公开(公告)号：US20240249758A1

公开(公告)日：2024-07-25

申请号：US18623355

申请日：2024-04-01

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave ,  Dirgha Khatri ,  Elancheren Durai ,  Quincy R. Holton ,  Timothy M. Hollis ,  Matthew B. Leslie ,  Baekkyu Choi ,  Boe L. Holbrook ,  Yogesh Sharma ,  Scott R. Cyr

IPC: G11C8/18 ,  G11C7/10 ,  G11C8/06 ,  G11C8/12

CPC classification number: G11C8/18 ,  G11C7/1096 ,  G11C8/06 ,  G11C8/12

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which clock trees can be separately optimized to provide a coarse alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal), and/or in which individual memory devices can be isolated for fine-tuning of device-specific alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal). Moreover, individual memory devices can be isolated for fine-tuning of device-specific equalization of a command/address signal (and/or a chip select signal or other control signal).

公开(公告)号：US20220171730A1

公开(公告)日：2022-06-02

申请号：US17108742

申请日：2020-12-01

Applicant: Micron Technology, Inc.

Inventor： William A. Lendvay ,  Scott R. Cyr

IPC: G06F13/38 ,  G06F30/392

Abstract: Methods, systems, and devices for pin mapping for memory devices are described. An apparatus may include a memory array, a plurality of pins, a selector, and a mapping component. The memory array may include a plurality of data lines coupled with a plurality of memory cells. The mapping component may be configured to map a set of data lines to a first set of pins when the selector reflects a first state and to a second set of pins when the selector reflects a second state. The first and second set of pins may have a same quantity of pins. The second set of pins may include pins that are otherwise unused in the second state. The mapping component may be configured to selectively couple unused pins to a fixed potential.

公开(公告)号：US20160240227A1

公开(公告)日：2016-08-18

申请号：US14624298

申请日：2015-02-17

Applicant: Micron Technology, Inc.

Inventor： Scott R. Cyr

IPC: G11C5/02 ,  H01L25/065 ,  G11C8/12 ,  G11C8/18 ,  H01L25/00 ,  G11C5/06

CPC classification number: G11C5/025 ,  G11C5/066 ,  G11C8/12 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06572

Abstract: Semiconductor device assemblies with semiconductor device packages configured to operate in mirror mode are disclosed herein. In one embodiment a semiconductor device assembly includes a first semiconductor device package attached to a front side of a support substrate, and a second semiconductor device package attached to a back side of the support substrate. The first device package includes a plurality of first package contacts having a first arrangement of corresponding pin assignments, and the second device package includes a plurality of second package contacts and a switch circuit operably coupled to the second package contacts. The switch circuit is configured to receive a switch signal via the support substrate, and to assign the second package contacts to either the first arrangement of corresponding pin assignments or a second arrangement of corresponding pin assignments based on the switch signal.

Abstract translation: 半导体器件组件，其半导体器件封装被配置为以镜像模式工作。 在一个实施例中，半导体器件组件包括附接到支撑衬底的前侧的第一半导体器件封装和附接到支撑衬底的背侧的第二半导体器件封装。 第一器件封装包括具有相应引脚分配的第一布置的多个第一封装触点，并且第二器件封装包括多个第二封装触点和可操作地耦合到第二封装触点的开关电路。 开关电路被配置为经由支撑衬底接收开关信号，并且将第二封装触点分配给相应引脚分配的第一布置或基于开关信号的相应引脚分配的第二布置。