An array substrate includes: a base; gate lines and data lines on the base; multiple pixel units each including a thin film transistor; first and second conductive layers with a first insulating layer therebetween. The first conductive layer includes a first wiring pattern, the second conductive layer includes a first interconnection pattern, orthographic projections of the first wiring pattern and the first interconnection pattern on the base are at least partially overlapped. The first wiring pattern is connected with the first interconnection pattern through a via hole. Each of part of data lines is located in the first conductive layer and has an auxiliary line formed by the first interconnection pattern in the second conductive layer. The first wiring pattern includes the data lines; at least one of the data line and the first interconnection pattern is connected to a source of the thin film transistor.