In a memory cell including a first gate insulating layer 5 and a first gate conductor layer 6 surrounding a pillar-shaped P layer 3a standing on a P layer substrate 1, a second gate insulating layer 9 in contact with a P layer 3b in contact with an upper surface of the P layer 3a, and N+ layers 11a and 11b at both ends of the P layer 3b and a MOS transistor including a pillar-shaped P layer 3aa standing on a P layer substrate 1a connecting to the same P layer substrate 1, a third gate insulating layer 9a in contact with the P layer 3aa, a third gate conductor layer 10a, and N+ layers 11aa and 11ba at both ends of a P layer 3ba, bottom portions of the P layer 3b and the P layer 3ba are located at substantially the same position.