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公开(公告)号：US20240196591A1
公开(公告)日：2024-06-13
申请号：US18537189
申请日：2023-12-12
发明人： Masakazu KAKUMU , Koji SAKUI , Nozomu HARADA
IPC分类号： H10B12/00 , G11C11/404 , G11C11/4096
CPC分类号： H10B12/20 , G11C11/404 , G11C11/4096
摘要： A memory device includes an n-layer 3a formed on a p-layer 1 of a substrate; an n-layer 3b extending in a vertical direction with a columnar p-layer 4 placed thereon; an insulating layer 2; a gate insulating layer 5; a gate conductor layer 22; an insulating layer 6; and a MOSFET made up of a p-layer 8, a gate insulating layer 9, n+ layers 7a and 7b, and a gate conductor layer 10. The n+ layers 7a and 7b, the gate conductor layers 5 and 10, and n-layer 3a are connected to a source line, bit line, plate line, and word line, and control line, respectively. Data retention operation is performed by controlling voltages applied to the respective layers to hold positive hole groups generated in the MOSFET, and data erase operation is performed to remove positive holes accumulated in the p-layer.
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公开(公告)号：US20230309287A1
公开(公告)日：2023-09-28
申请号：US18187764
申请日：2023-03-22
发明人： Masakazu KAKUMU , Koji SAKUI , Nozomu HARADA
IPC分类号： H10B12/00 , G11C11/404 , G11C11/4096
CPC分类号： H10B12/20 , G11C11/404 , G11C11/4096
摘要： A p layer is a semiconductor base material. An n+ layer is disposed on one extension side of the layer. An n+ layer is disposed on the opposite side in contact with the layer. A gate insulating layer partially covers the layers. A gate conductor layer is disposed in contact with the layer. A gate insulating layer partially covers the layers. A gate conductor layer is disposed in electrical separation from the layer. Memory operation is performed by applying voltage to each of the layers. In this case, the gate capacitance of a MOS structure constituted by the layers per unit area is smaller than that of a MOS structure constituted by the layers.
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公开(公告)号：US20230298659A1
公开(公告)日：2023-09-21
申请号：US18184309
申请日：2023-03-15
发明人： Masakazu KAKUMU , Koji Sakui , Nozomu Harada
IPC分类号： G11C11/409 , H10B12/00
CPC分类号： G11C11/409 , H10B12/20
摘要： A p layer extending in a direction horizontal to a substrate is provided separately from the substrate. An n+ layer is provided on one side of the layer. A gate insulating layer partially covers the layers. A gate conductor layer partially covers the layer. A gate insulating layer partially covering the layer is provided separately from the layer. A gate conductor layer partially covers the layer. An n+ layer is provided at part of the p layer between the layers. The layers are connected to a bit line, a source line, a word line, and a plate line, respectively. Memory operation of a dynamic flash memory cell is performed by manipulating voltage of each line.
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公开(公告)号：US20230247820A1
公开(公告)日：2023-08-03
申请号：US18162446
申请日：2023-01-31
发明人： Masakazu KAKUMU , Koji SAKUI , Nozomu HARADA
IPC分类号： H10B12/00
CPC分类号： H10B12/20
摘要： On a substrate, a first semiconductor layer 1 is formed; from a portion of the layer 1, a first impurity layer 3 extends vertically, and a second semiconductor layer 4 is disposed on the layer 3; side walls of the layers 3 and 4 and the layer 1 are covered with a first gate insulating layer 2; in the resultant grooves, a first gate conductor layer 22 and a second insulating layer 6 are disposed; over the second semiconductor layer 4, layers are disposed that are a third semiconductor layer 8, an n+ layer 7a connecting to a source line SL and an n+ layer 7b connecting to a bit line BL that are disposed on both sides of the layer 8, a second gate insulating layer 9 formed so as to cover the layer 8, and a second gate conductor layer 10 connecting to a word line WL.
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公开(公告)号：US20240081039A1
公开(公告)日：2024-03-07
申请号：US18461914
申请日：2023-09-06
发明人： Koji SAKUI , Masakazu KAKUMU , Nozomu HARADA
IPC分类号： H10B12/00 , G11C11/404 , G11C11/408 , G11C11/4091 , G11C11/4096
CPC分类号： H10B12/20 , G11C11/404 , G11C11/4087 , G11C11/4091 , G11C11/4096
摘要： A memory device includes pages in a column direction on a substrate and memory cells in each page in a row direction in plan view. Each memory cell includes a semiconductor base, first and second impurity regions, connected to a source line and a bit line, respectively, at both ends of the semiconductor base, and first and second gate conductor layers, one of which is connected to a word line and the other of which is connected to a plate line. A continuous operation of a page erase operation and a page write operation is performed by controlling voltages applied to the source line, the bit line, the word line, and the plate line without performing a reset operation for returning the voltage applied to the plate line to a ground voltage.
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公开(公告)号：US20230402090A1
公开(公告)日：2023-12-14
申请号：US18333674
申请日：2023-06-13
发明人： Koji SAKUI , Masakazu KAKUMU , Nozomu HARADA
IPC分类号： G11C11/4096 , G11C11/408 , G11C11/4091 , H10B12/00
CPC分类号： G11C11/4096 , G11C11/4087 , G11C11/4091 , H10B12/20
摘要： A memory device includes pages each including memory cells arranged in columns in plan view on a substrate, and voltages applied to first and second gate conductor layers and first and second impurity regions in each memory cell are controlled to retain a group of positive holes, generated by an impact ionization phenomenon, inside a semiconductor body. The first and second impurity regions are connected to source and bit lines, the first and second gate conductor layers are connected to word and plate lines, and voltages applied to these lines are controlled to perform a page write operation, a page erase operation, and a page read operation. In the page write operation, the group of positive holes are retained inside the semiconductor body at a first time, and a page write post-processing operation of making a group of excess positive holes disappear is performed at a second time.
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公开(公告)号：US20230284432A1
公开(公告)日：2023-09-07
申请号：US18176680
申请日：2023-03-01
发明人： Nozomu HARADA , Masakazu KAKUMU , Koji SAKUI
CPC分类号： H10B12/20 , H01L29/7841
摘要： Si bodies 24aa to 24ad, 24ba to 24bd, and 45a to 45d are disposed parallel to a substrate 20 and are adjacent to each other in a horizontal direction at regular intervals. A HfO2 layer 27b surrounds the Si bodies 24aa to 45d. TiN layers 34a to 34d surround the HfO2 layer 27b, are isolated from each other, and are each formed of portions contiguous in the horizontal direction. The Si bodies 45a to 45d are formed stepwise in cross-sectional view in the terminating end in the horizontal direction. Metal wiring layers 52a to 52d are connected to the TiN layers 34a to 34d and extend up to above an insulating layer 50 through contact holes 51a to 51d extending in a vertical direction from the terminating ends of the TiN layers 34a to 34d. The metal wiring layers 52a to 52d are connected to word lines WL1 to WL4.
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公开(公告)号：US20230115447A1
公开(公告)日：2023-04-13
申请号：US17903502
申请日：2022-09-06
发明人： Masakazu KAKUMU , Koji SAKUI , Nozomu HARADA
摘要： A groove is formed in a first semiconductor layer 1, a sidewall of the groove is coated with a first insulating film 2, a first impurity layer 3 and a second impurity layer 4 thereon are disposed in the groove, a second semiconductor layer 7 is disposed on the second impurity layer, a first semiconductor is disposed at the other part, an n+ layer 6a and an n+ layer 6c are positioned at respective ends of the second semiconductor layer 7 and connected to a source line SL and a bit line BL, respectively, a first gate insulating layer 8 is formed on the second semiconductor layer 7, and a first gate conductor layer 9 is connected to a word line WL. Voltage applied to the source line SL, a plate line PL connected to the first semiconductor layer 1, the word line WL, and the bit line BL is controlled to perform data holding operation of holding, near the gate insulating layer, holes generated by an impact ionization phenomenon in a channel region 12 of the second semiconductor layer or by gate-induced drain leakage current, and data erase operation of removing the holes from the channel region 12.
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公开(公告)号：US20240349482A1
公开(公告)日：2024-10-17
申请号：US18624515
申请日：2024-04-02
发明人： Masakazu KAKUMU , Koji SAKUI , Nozomu HARADA
IPC分类号： H10B12/00 , G11C11/404 , G11C11/4096
CPC分类号： H10B12/20 , G11C11/404 , G11C11/4096
摘要： Provided is a memory semiconductor device including an access transistor, in which an n-type semiconductor layer is formed on a p-type semiconductor region provided on a substrate; a first p-type semiconductor layer that has a columnar shape exists in a vertical direction from a portion of the n-type semiconductor layer; an insulating layer that covers a portion of the first p-type semiconductor layer and a portion of the n-type semiconductor layer exists; in contact therewith, a first gate insulating layer contacts the first p-type semiconductor layer; in contact with the first gate insulating layer, a first gate conductive layer exists; a second p-type semiconductor layer whose surface is recessed exists on the first p-type semiconductor layer; a second gate insulating layer and a second gate conductive layer exist thereabove; and an n+ layer is provided on both sides thereof.
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公开(公告)号：US20240321342A1
公开(公告)日：2024-09-26
申请号：US18609167
申请日：2024-03-19
发明人： Masakazu KAKUMU , Koji Sakui , Nozomu Harada
IPC分类号： G11C11/4096 , H01L23/528 , H10B12/00
CPC分类号： G11C11/4096 , H01L23/5283 , H10B12/20
摘要： A memory device includes a first n-layer formed on a first p-layer on a substrate; a second n-layer extending vertically with a second p-layer placed thereon; a first insulating layer partially covering the n-layers; a first gate insulating layer in contact with the first insulating layer; a first gate conductor layer in contact with the gate insulating layer and first insulating layer; a second insulating layer in contact with the first gate conductor layer; and a MOSFET formed of a third p-layer placed on the second p-layer, a second gate insulating layer placed atop the third p-layer, n+ layers placed on opposite ends of the third p-layer, and a second gate conductor layer. Contact area between the second p-layer and second n-layer is smaller than a cross-section of the second p-layer. A write/erase operation is performed by applying voltages to the n+ layers, gate conductor layers, and first n-layer.
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