Invention Publication
- Patent Title: METHOD FOR FORMING A SEMICONDUCTOR DEVICE
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Application No.: US18538879Application Date: 2023-12-13
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Publication No.: US20240204080A1Publication Date: 2024-06-20
- Inventor: Boon Teik Chan , Hsiao-Hsuan Liu , Pieter Schuddinck
- Applicant: IMEC VZW , Katholieke Universiteit Leuven
- Applicant Address: BE Leuven
- Assignee: IMEC VZW,Katholieke Universiteit Leuven
- Current Assignee: IMEC VZW,Katholieke Universiteit Leuven
- Current Assignee Address: BE Leuven
- Priority: EP 214882.7 2022.12.20
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/8238 ; H01L27/092 ; H01L29/06 ; H01L29/417 ; H01L29/423 ; H01L29/775 ; H01L29/786

Abstract:
A method for forming a semiconductor device is provided. The method includes: forming, over a substrate, a stacked transistor structure comprising: a bottom channel structure and a top channel structure, a gate structure extending across the bottom and top channel structures, a first and a second bottom S/D structure on the bottom channel structure, and a first and a second top S/D structure on the top channel structure; forming a first and a second bottom S/D contact on the first and the second bottom S/D structures; forming a contact isolation layer capping the first and second bottom S/D contacts, and covering the capped first and second bottom S/D contacts with an ILD layer; forming a first contact trench; forming a second contact trench; and forming a first top S/D contact.
Information query
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