Invention Publication
- Patent Title: GATE STRUCTURE AND PATTERNING METHOD
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Application No.: US18615403Application Date: 2024-03-25
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Publication No.: US20240234214A1Publication Date: 2024-07-11
- Inventor: Lung-Kun Chu , Mao-Lin Huang , Wei-Hao Wu , Kuo-Cheng Chiang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- The original application number of the division: US16381232 2019.04.11
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L21/3213 ; H01L27/092 ; H01L29/40 ; H01L29/423

Abstract:
A semiconductor device includes a semiconductor substrate; a plurality of channel regions, including a p-type channel region and an n-type channel region, disposed over the semiconductor substrate; and a gate structure. The gate structure includes a gate dielectric layer disposed over the plurality of channel regions and a work function metal (WFM) structure disposed over the gate dielectric layer. The WFM structure includes an n-type WFM layer over the n-type channel region and not over the p-type channel region and further includes a p-type WFM layer over both the n-type WFM layer and the p-type channel region. The gate structure further includes a fill metal layer disposed over the WFM structure and in direct contact with the p-type WFM layer.
Information query
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