Invention Publication
- Patent Title: MULTI-GATE DEVICES AND FABRICATING THE SAME WITH ETCH RATE MODULATION
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Application No.: US18623143Application Date: 2024-04-01
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Publication No.: US20240258407A1Publication Date: 2024-08-01
- Inventor: Chih-Ching Wang , Chung-I Yang , Jon-Hsu Ho , Wen-Hsing Hsieh , Kuan-Lun Cheng , Chung-Wei Wu , Zhiqiang Wu
- Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
- Current Assignee Address: TW Hsin-Chu
- The original application number of the division: US16901881 2020.06.15
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/8234 ; H01L29/417 ; H01L29/78

Abstract:
The present disclosure provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes channel members vertically stacked above a substrate, a gate structure engaging the channel members, a gate sidewall spacer disposed on a sidewall of the gate structure, an epitaxial feature abutting end portions of the channel members, and inner spacers interposing the gate structure and the epitaxial feature. The end portion of at least one of the channel members includes a first dopant. A concentration of the first dopant in the end portion of the at least one of the channel members is higher than in a center portion of the at least one of the channel members. The concentration of the first dopant in the end portion of the at least one of the channel members is higher than in an outer portion of the epitaxial feature.
Information query
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