Invention Publication
- Patent Title: NORMALLY-ON GALLIUM NITRIDE BASED TRANSISTOR WITH P-TYPE GATE
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Application No.: US18625366Application Date: 2024-04-03
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Publication No.: US20240274705A1Publication Date: 2024-08-15
- Inventor: Chang Soo Suh , Jungwoo Joh , Dong Seup Lee , Shoji Wada , Karen Hildegard Ralston Kirmse
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- The original application number of the division: US17108892 2020.12.01
- Main IPC: H01L29/778
- IPC: H01L29/778 ; B82Y30/00 ; B82Y40/00 ; H01L29/20 ; H01L29/66

Abstract:
A semiconductor device includes a gallium nitride based low threshold depletion mode transistor (GaN FET) with a threshold potential between −10 volts and −0.5 volts. The GaN FET has a channel layer of III-N semiconductor material including gallium and nitrogen that supports a two-dimensional electron gas (2DEG). The GaN FET has a barrier layer of III-N semiconductor material including aluminum and nitrogen over the channel layer. The GaN FET further has a p-type gate of III-N semiconductor material including gallium and nitrogen. A bottom surface of the gate, adjacent to the barrier layer, does not extend past a top surface of the barrier layer, located opposite from the channel layer. The GaN FET is free of a dielectric layer between the gate and the barrier layer.
Information query
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