A semiconductor device according to an embodiment includes a substrate, first and second pillar electrodes extending along a vertical direction substantially perpendicular to a surface of the substrate, and a plurality of memory cells disposed between the first and second pillar electrodes. Each of the plurality of memory cells includes first and second shared device layers that are disposed adjacent to the first and second pillar electrodes, respectively, and extend along the vertical direction, first and second base device layers disposed between the first and second shared device layers, and a control gate electrode disposed on one of the first and second base device layers. Both first and second base device layers are disposed on a plane over the substrate and substantially parallel to the surface of the substrate.