公开(公告)号：US20240260252A1

公开(公告)日：2024-08-01

申请号：US18629907

申请日：2024-04-08

申请人： Zeno Semiconductor, Inc.

发明人： Yuniarto Widjaja ,  Jin-Woo Han ,  Benjamin S. Louie

IPC分类号： H10B12/00 ,  G11C11/404 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  H01L29/08 ,  H01L29/10 ,  H01L29/36 ,  H01L29/70 ,  H01L29/73 ,  H01L29/732 ,  H01L29/78 ,  H10B12/10 ,  H10B41/35

CPC分类号： H10B12/20 ,  G11C11/404 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3427 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/70 ,  H01L29/73 ,  H01L29/7302 ,  H01L29/7841 ,  H10B12/10 ,  H10B41/35 ,  H01L29/1004 ,  H01L29/732

摘要： A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.

公开(公告)号：US20230343392A1

公开(公告)日：2023-10-26

申请号：US18214714

申请日：2023-06-27

申请人： Zeno Semiconductor, Inc.

发明人： Yuniarto Widjaja

IPC分类号： G11C14/00 ,  G11C11/14 ,  G11C11/404 ,  G11C11/56 ,  G11C13/00 ,  H01L29/78 ,  H10B12/00 ,  H10B12/10 ,  H10B63/00 ,  H10N70/20 ,  H10N70/00 ,  G06F3/06 ,  G11C11/402 ,  G11C11/4067 ,  H01L27/12

CPC分类号： G11C14/0045 ,  G11C11/14 ,  G11C11/404 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0033 ,  H01L29/7841 ,  H10B12/00 ,  H10B12/10 ,  H10B12/20 ,  H10B12/50 ,  H10B63/00 ,  H10B63/32 ,  H10B63/80 ,  H10N70/24 ,  H10N70/231 ,  H10N70/235 ,  H10N70/245 ,  H10N70/826 ,  H10N70/841 ,  H10N70/882 ,  H10N70/8833 ,  H10N70/8836 ,  G06F3/0619 ,  G06F3/0647 ,  G06F3/0685 ,  G11C11/4026 ,  G11C11/4067 ,  G11C13/004 ,  G11C13/0069 ,  H01L27/1203 ,  G11C2211/4016 ,  G11C2211/5643 ,  G11C2213/31 ,  G11C2213/32 ,  H10N70/8828 ,  G11C2013/0045 ,  G11C2013/0078

摘要： Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.

公开(公告)号：US11948637B2

公开(公告)日：2024-04-02

申请号：US18088192

申请日：2022-12-23

申请人： Zeno Semiconductor, Inc.

发明人： Yuniarto Widjaja

IPC分类号： G11C14/00 ,  G11C11/402 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/56 ,  G11C13/00 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H10B12/00 ,  H10B12/10 ,  H10B63/00 ,  H10B99/00 ,  H10N70/00 ,  H10N70/20 ,  G11C16/04

CPC分类号： G11C14/0045 ,  G11C11/4026 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/56 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/0097 ,  G11C14/0018 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/7881 ,  H10B12/10 ,  H10B12/20 ,  H10B63/00 ,  H10B99/00 ,  H10N70/231 ,  H10N70/883 ,  G11C16/0416 ,  G11C2211/4016 ,  G11C2213/76 ,  G11C2213/79 ,  H10N70/8828

摘要： A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.

公开(公告)号：US20230345700A1

公开(公告)日：2023-10-26

申请号：US18216359

申请日：2023-06-29

申请人： Zeno Semiconductor, Inc.

发明人： Yuniarto Widjaja ,  Zvi Or-Bach

IPC分类号： H10B12/00 ,  G11C14/00 ,  H01L29/66 ,  H01L29/788 ,  G11C11/404 ,  G11C11/39 ,  H10B12/10 ,  H01L29/78 ,  H01L29/772 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4094 ,  H01L23/528 ,  H01L29/10 ,  G11C11/4096 ,  G11C11/4099 ,  H01L29/08

CPC分类号： H10B12/20 ,  G11C14/0018 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  G11C11/404 ,  G11C11/39 ,  H10B12/10 ,  H01L29/7841 ,  H01L29/772 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4094 ,  H01L23/528 ,  H01L29/1095 ,  G11C11/4096 ,  G11C11/4099 ,  H01L29/0821 ,  H01L29/1004 ,  G11C11/4026

摘要： An IC may include an array of memory cells formed in a semiconductor, including memory cells arranged in rows and columns, each memory cell may include a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, wherein the floating body region is bounded on a first side by a first insulating region having a first thickness and on a second side by a second insulating region having a second thickness, and a gate region above the floating body region and the second insulating region and is insulated from the floating body region by an insulating layer; and control circuitry configured to provide electrical signals to said buried region.

公开(公告)号：US20240276741A1

公开(公告)日：2024-08-15

申请号：US18356162

申请日：2023-07-20

申请人： SK hynix Inc.

发明人： Bo Min PARK ,  Seung Wook RYU

IPC分类号： H10B99/00 ,  H01L29/74 ,  H10B12/10

CPC分类号： H10B99/20 ,  H01L29/7404 ,  H10B12/10

摘要： A semiconductor device according to an embodiment includes a substrate, first and second pillar electrodes extending along a vertical direction substantially perpendicular to a surface of the substrate, and a plurality of memory cells disposed between the first and second pillar electrodes. Each of the plurality of memory cells includes first and second shared device layers that are disposed adjacent to the first and second pillar electrodes, respectively, and extend along the vertical direction, first and second base device layers disposed between the first and second shared device layers, and a control gate electrode disposed on one of the first and second base device layers. Both first and second base device layers are disposed on a plane over the substrate and substantially parallel to the surface of the substrate.

公开(公告)号：US20240136392A1

公开(公告)日：2024-04-25

申请号：US18491779

申请日：2023-10-21

申请人： ASM IP Holding B.V.

发明人： Alessandra Leonhardt ,  Michael Eugene Givens ,  Giuseppe Alessio Verni ,  Qi Xie

IPC分类号： H10B12/10

CPC分类号： H01L28/75

摘要： Methods of processing a substrate and related structures and systems. Described methods comprise forming a distal dipole layer on to a distal material layer; forming a high-k dielectric on the distal dipole layer; and, forming a proximal dipole layer on the high-k dielectric.

公开(公告)号：US11727987B2

公开(公告)日：2023-08-15

申请号：US17693751

申请日：2022-03-14

申请人： Zeno Semiconductor, Inc.

发明人： Yuniarto Widjaja

IPC分类号： G11C14/00 ,  G11C11/14 ,  G11C11/404 ,  G11C11/56 ,  G11C13/00 ,  H01L29/78 ,  H10B12/00 ,  H10B12/10 ,  H10B63/00 ,  H10N70/20 ,  H10N70/00 ,  G06F3/06 ,  G11C11/402 ,  G11C11/4067 ,  H01L27/12

CPC分类号： G11C14/0045 ,  G06F3/0619 ,  G06F3/0647 ,  G06F3/0685 ,  G11C11/14 ,  G11C11/404 ,  G11C11/4026 ,  G11C11/4067 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0007 ,  G11C13/0033 ,  G11C13/0069 ,  H01L27/1203 ,  H01L29/7841 ,  H10B12/00 ,  H10B12/10 ,  H10B12/20 ,  H10B12/50 ,  H10B63/00 ,  H10B63/32 ,  H10B63/80 ,  H10N70/231 ,  H10N70/235 ,  H10N70/24 ,  H10N70/245 ,  H10N70/826 ,  H10N70/841 ,  H10N70/882 ,  H10N70/8833 ,  H10N70/8836 ,  G11C2013/0045 ,  G11C2013/0078 ,  G11C2211/4016 ,  G11C2211/5643 ,  G11C2213/31 ,  G11C2213/32 ,  H10N70/8828

摘要： Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.

公开(公告)号：US20240322023A1

公开(公告)日：2024-09-26

申请号：US18578745

申请日：2022-07-12

申请人： IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)

发明人： Sang Dong YOO ,  Jea Gun PARK ,  Tae Hun SHIM ,  Min Won KIM ,  Byoung Seok LEE ,  Ji Hun KIM

IPC分类号： H01L29/74 ,  H01L29/06 ,  H01L29/08 ,  H10B12/10

CPC分类号： H01L29/7408 ,  H01L29/0692 ,  H01L29/0834 ,  H01L29/0839 ,  H10B12/10

摘要： The present invention relates to a thyristor having a vertical structure and a cross-point memory array including the same. The thyristor having a vertical structure according to one embodiment may include a semiconductor core with an insulating film formed on the outer peripheral surface thereof, and a plurality of metal layers formed on the insulating film. In the semiconductor core, at least one layer of a base layer and an emitter layer may be formed on a region corresponding to each of the metal layers based on the charge plasma phenomenon due to the difference in work function with the metal layers.

公开(公告)号：US20240242759A1

公开(公告)日：2024-07-18

申请号：US18319513

申请日：2023-05-18

申请人： MACRONIX INTERNATIONAL CO., LTD.

发明人： Wei-Chen CHEN ,  Hang-Ting LUE

IPC分类号： G11C11/4097 ,  G11C11/4067 ,  H10B12/10

CPC分类号： G11C11/4097 ,  G11C11/4067 ,  H10B12/10

摘要： A memory structure and methods for operating memory structures are provided. The memory structure includes a first, a second and a third gate structures disposed along a first direction and separated from each other, channel bodies having first ends and second ends, source regions separated from each other, having first conductivity types and connected to the first ends of the channel bodies respectively, drain regions separated from each other, having second conductivity types and connected to the second ends of the channel bodies respectively, and first side plugs disposed along a second direction, extending along a third direction, and electrically connected to the source regions and the channel bodies. The first gate structure includes island structures disposed along the second direction and extending along the third direction.

公开(公告)号：US20240234483A9

公开(公告)日：2024-07-11

申请号：US18491779

申请日：2023-10-22

申请人： ASM IP Holding B.V.

发明人： Alessandra Leonhardt ,  Michael Eugene Givens ,  Giuseppe Alessio Verni ,  Qi Xie

IPC分类号： H10B12/10

CPC分类号： H01L28/75

摘要： Methods of processing a substrate and related structures and systems. Described methods comprise forming a distal dipole layer on to a distal material layer; forming a high-k dielectric on the distal dipole layer; and, forming a proximal dipole layer on the high-k dielectric.