Invention Publication
- Patent Title: ROUTING FOR CHIP LAYOUT
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Application No.: US18657419Application Date: 2024-05-07
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Publication No.: US20240289530A1Publication Date: 2024-08-29
- Inventor: Shengming MA , Yue CHEN , Jianming WANG , Sainan HUAI , Shengyu ZHANG , Xuemeng WANG , Xiong XU , Yanghepu LI
- Applicant: Tencent Technology (Shenzhen) Company Limited
- Applicant Address: CN Shenzhen
- Assignee: Tencent Technology (Shenzhen) Company Limited
- Current Assignee: Tencent Technology (Shenzhen) Company Limited
- Current Assignee Address: CN Shenzhen
- Priority: CN 2210887533.0 2022.07.26
- Main IPC: G06F30/3953
- IPC: G06F30/3953

Abstract:
In a routing method, an initial chip layout and routing planning information corresponding to the initial chip layout are obtained. The routing planning information includes planning information of a first site in the initial chip layout. The planning information indicates a location region, a routing orientation, and a predefined connection path. A first end of the predefined connection path is connected to the first site. According to the location region and the routing orientation, a first route segment connecting a second site of the initial chip layout and a second end of the predefined connection path is determined. According to the predefined connection path, a second route segment connecting the second end of the predefined connection path and the first site is determined. According to the first route segment and the second route segment, a connection route between the second site and the first site is generated.
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