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1.发明申请公开(公告)号：US20250061258A1
公开(公告)日：2025-02-20
申请号：US18770482
申请日：2024-07-11
Inventor： Xingyu MA , Shaogang HAO , Shengyu ZHANG
IPC: G06F30/392 , G06F30/398
Abstract: A method for determining a parameter of a layout quality detection tool performed by an electronic device. The method includes: performing a quality detection on an original chip layout by using a layout quality detection tool to obtain quality indicators corresponding to first base values; when the quality indicators do not meet a reference condition, determining a first reference value from a plurality of first candidate values based on the quality indicators, and determining a plurality of second base values based on the plurality of first base values and the first reference value; performing a quality detection on the original chip layout by using the tool to obtain quality indicators corresponding to the second base values; and when the quality indicators meet the reference condition, determining a target value of the target parameter based on the second base values for improving the accuracy of the tool.
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公开(公告)号：US20240339175A1
公开(公告)日：2024-10-10
申请号：US18745916
申请日：2024-06-17
Inventor： Lixue CHENG , Ziyi YANG , Benben LIAO , Shengyu ZHANG
Abstract: Provided is an object determining method performed by a computer device, relating to the technical field of artificial intelligence. The method includes: acquiring index prediction values of objects in a first object set on a preset index respectively; determining, based on index experimental values and object features of the objects in the first object set on the preset index, a mapping relationship between the preset index and the object features; selecting, from the first object set, objects with the index prediction values satisfying index value screening conditions to obtain a second object set; and determining a target object meeting index requirements of the preset index from the second object set based on the mapping relationship.
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公开(公告)号：US20240289530A1
公开(公告)日：2024-08-29
申请号：US18657419
申请日：2024-05-07
Inventor： Shengming MA , Yue CHEN , Jianming WANG , Sainan HUAI , Shengyu ZHANG , Xuemeng WANG , Xiong XU , Yanghepu LI
IPC: G06F30/3953
CPC classification number: G06F30/3953
Abstract: In a routing method, an initial chip layout and routing planning information corresponding to the initial chip layout are obtained. The routing planning information includes planning information of a first site in the initial chip layout. The planning information indicates a location region, a routing orientation, and a predefined connection path. A first end of the predefined connection path is connected to the first site. According to the location region and the routing orientation, a first route segment connecting a second site of the initial chip layout and a second end of the predefined connection path is determined. According to the predefined connection path, a second route segment connecting the second end of the predefined connection path and the first site is determined. According to the first route segment and the second route segment, a connection route between the second site and the first site is generated.
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公开(公告)号：US20240265187A1
公开(公告)日：2024-08-08
申请号：US18638544
申请日：2024-04-17
Inventor： Shengming MA , Yue CHEN , Jianming WANG , Sainan HUAI , Shengyu ZHANG , Xiong XU
IPC: G06F30/3953
CPC classification number: G06F30/3953
Abstract: This application discloses a circuit layout routing method performed by a computer device, and relates to the field of micro-nano processing technologies. The method includes: obtaining position information of at least one routing point in a circuit layout from routing planning information of the circuit layout; calculating, based on the position information, a turning starting position and a turning radius corresponding to each of the at least one routing point; and generating a routing path through the at least one routing point based on the turning starting position and the turning radius, the routing path turning at the turning starting position w ith the turning radius. The foregoing solution expands an applicable scenario of an automatic routing algorithm.
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公开(公告)号：US20240242784A1
公开(公告)日：2024-07-18
申请号：US18619052
申请日：2024-03-27
Inventor： Lixue CHENG , Jonathan Pradana MAILOA , Shengyu ZHANG
Abstract: This application discloses a molecular energy prediction method performed by a computer device. The method includes: obtaining first prediction energy of a target molecule and a quantum operator of the target molecule by using a first calculation method, the quantum operator of the target molecule being configured for describing a wave function of the target molecule; predicting energy information of the target molecule through a molecular energy prediction model and according to the quantum operator of the target molecule; and determining final prediction energy of the target molecule according to the first prediction energy and the energy information. The first prediction energy of the target molecule and the quantum operator of the target molecule obtained through the first calculation method are used to predict the final prediction energy of the target molecule according to the molecular energy prediction model.
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Patent Agency Ranking
6.发明公开公开(公告)号：US20230351237A1
公开(公告)日：2023-11-02
申请号：US18202402
申请日：2023-05-26
Inventor： Pei YUAN , Shengyu ZHANG
Abstract: The present disclosure relates to a quantum state preparation circuit generation method and apparatus, a quantum chip, and an electronic device. The quantum chip may be applied to various intelligent terminals and on-board devices. The method includes: determining a first unitary operator respectively encoding rc qubits and rt qubits into a control register and a target register; acquiring at least two second unitary operators for performing phase shifting on the n qubits; determining a third unitary operator for replacing a qubit of the control register and a qubit of the target register; generating diagonal unitary matrix quantum circuits based on the first, second, third, fourth unitary operators, and a diagonal unitary matrix operator; combining the diagonal unitary matrix quantum circuits with a single-bit gate to obtain at least two uniform control gates; and combining the at least two uniform control gates into a quantum state preparation circuit.
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公开(公告)号：US20220130784A1
公开(公告)日：2022-04-28
申请号：US17571780
申请日：2022-01-10
Inventor： Wenlong ZHANG , Chuhong YANG , Yarui ZHENG , Shengyu ZHANG
IPC: H01L23/00
Abstract: This disclosure discloses a method for preparing an indium pillar, a chip substrate and a chip. The method includes: applying a first photoresist layer on a substrate; applying a second photoresist layer on the first photoresist layer; covering a part of a surface of the second photoresist layer; underexposing the part of the second photoresist layer to obtain a processed second photoresist layer; developing and fixing the processed second photoresist layer to form an undercut structure; etching the first photoresist layer through the undercut structure to form an expose area; and depositing an indium material on the exposed area to form an indium pillar solder.
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公开(公告)号：US20220058435A1
公开(公告)日：2022-02-24
申请号：US17476754
申请日：2021-09-16
Inventor： Songlian OU , Changyu HSIEH , Shengyu ZHANG
Abstract: A data classification method and system, and a classifier training method and system are disclosed in the embodiments of the present disclosure, belonging to the field of artificial intelligence (AI), cloud technologies, and quantum technologies. The method includes: providing to-be-classified data to a quantum computer; performing feature mapping on the to-be-classified data by using a quantum circuit to obtain a quantum state of the to-be-classified data; determining an estimation result according to a boundary vector of a classifier, the quantum state of the to-be-classified data, and a quantum state of index information corresponding to the boundary vector; transmitting the estimation result to a classical computer. The quantum state of the index information refers to a superposition of feature maps of training data used by the classifier during training; and determining a classification result corresponding to the to-be-classified data according to the estimation result.
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9.发明申请公开(公告)号：US20250053079A1
公开(公告)日：2025-02-13
申请号：US18786309
申请日：2024-07-26
Inventor： Xingyu MA , Shaogang HAO , Shengyu ZHANG
IPC: G03F1/70
Abstract: This application provides a mask generation model training method performed by a computer device, the method including: obtaining a predicted mask of a target layout of a chip sample; inputting the predicted mask into a photolithography physical model to obtain a wafer pattern corresponding to the predicted mask; determining complexity of the predicted mask of the target layout based on a sum of perimeters of a plurality of patterns included in the target layout of the chip sample and a perimeter of the predicted mask of the target layout; and adjusting a parameter of the mask generation model based on the target layout of the chip sample, the wafer pattern corresponding to the predicted mask of the target layout, the mask of the target layout, the predicted mask of the target layout, and the complexity of the predicted mask of the target layout to obtain a trained mask generation model.
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公开(公告)号：US20240334843A1
公开(公告)日：2024-10-03
申请号：US18735054
申请日：2024-06-05
Inventor： Jingjing HU , Maochun DAI , Shuoming AN , Wenlong ZHANG , Dengfeng LI , Shengyu ZHANG
CPC classification number: H10N60/0912 , G03F7/0035 , G03F7/40 , G03F7/70025 , G03F7/70383 , H03F7/00 , H03F19/00 , H10N60/12 , G03F7/094
Abstract: A chip preparation method and system, and a chip are provided. The method includes: preparing, by using a laser direct writing exposure manner, a first underlying circuit of an impedance Josephson parametric amplifier and a second underlying circuit for testing, to obtain a first chip product; generating, on the first chip product by using the laser direct writing exposure manner, a photoresist structure for preparing a Josephson junction; cutting, from the first chip product, a second chip product on which the second underlying circuit is located and a third chip product on which the first underlying circuit is located; preparing a Josephson junction sample based on a photoresist structure corresponding to the second underlying circuit, to obtain an oxidation condition; and preparing, according to the oxidation condition, the Josephson junction based on a photoresist structure corresponding to the first underlying circuit.
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