- 专利标题: LIMITER CIRCUIT, MATCHING NETWORK, AND POWER AMPLIFIER CIRCUIT
-
申请号: US18655725申请日: 2024-05-06
-
公开(公告)号: US20240291442A1公开(公告)日: 2024-08-29
- 发明人: Shingo YANAGIHARA
- 申请人: Murata Manufacturing Co., Ltd.
- 申请人地址: JP Kyoto
- 专利权人: Murata Manufacturing Co., Ltd.
- 当前专利权人: Murata Manufacturing Co., Ltd.
- 当前专利权人地址: JP Kyoto
- 优先权: JP 21188038 2021.11.18
- 主分类号: H03F1/52
- IPC分类号: H03F1/52 ; H03F1/56 ; H03F3/21
摘要:
A limiter circuit includes: one or a plurality of first diodes having an anode electrically connected to a signal line through which a high-frequency signal passes, and a cathode electrically connected to a node, the plurality of first diodes being connected in series; a transistor having a source-drain path or an emitter-collector path electrically connected between a reference potential and the node, and a gate or a base to which a control voltage or a control current is input; and a first constant current source that outputs a first constant current to the node.
信息查询