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公开(公告)号：US20240291442A1
公开(公告)日：2024-08-29
申请号：US18655725
申请日：2024-05-06
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Shingo YANAGIHARA
CPC classification number: H03F1/52 , H03F1/565 , H03F3/21 , H03F2200/387 , H03F2200/426
Abstract: A limiter circuit includes: one or a plurality of first diodes having an anode electrically connected to a signal line through which a high-frequency signal passes, and a cathode electrically connected to a node, the plurality of first diodes being connected in series; a transistor having a source-drain path or an emitter-collector path electrically connected between a reference potential and the node, and a gate or a base to which a control voltage or a control current is input; and a first constant current source that outputs a first constant current to the node.
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公开(公告)号：US20180367105A1
公开(公告)日：2018-12-20
申请号：US16110028
申请日：2018-08-23
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Shingo YANAGIHARA
Abstract: A power amplifier module includes a first amplifier that amplifies an input signal to generate a first amplified signal and outputs the first amplified signal, a second amplifier that amplifies the first amplified signal to generate a second amplified signal and outputs the second amplified signal, and a matching network disposed between an output terminal of the first amplifier and an input terminal of the second amplifier. The first amplifier is provided on a first chip, and the second amplifier is provided on a second chip. The matching network has an impedance transformation characteristic adjustable in accordance with a control signal.
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公开(公告)号：US20210344312A1
公开(公告)日：2021-11-04
申请号：US17242815
申请日：2021-04-28
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Tsutomu KOBORI , Shingo YANAGIHARA , Yoshifumi TAKAHASHI , Hiroshi OKABE
Abstract: A power amplifier device includes a semiconductor substrate; a plurality of first transistors that are provided on the semiconductor substrate and receive input of a radio-frequency signal; a plurality of second transistors that are provided on the semiconductor substrate and electrically connected to the respective plurality of first transistors, and output a radio-frequency output signal obtained by amplifying the radio-frequency signal; a plurality of first bumps provided so as to overlay the respective plurality of first transistors; and a second bump provided away from the plurality of first bumps and provided so as not to overlay the plurality of first transistors and the plurality of second transistors. When viewed in plan from a direction perpendicular to a surface of the semiconductor substrate, a first transistor and a first bump, a second transistor, the second bump, a second transistor, and a first transistor and a first bump are arranged in sequence.
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公开(公告)号：US20130309985A1
公开(公告)日：2013-11-21
申请号：US13950576
申请日：2013-07-25
Applicant: MURATA MANUFACTURING CO., LTD.
Inventor： Kenji SAITO , Shingo YANAGIHARA , Tsuyoshi SATO , Syunji YOSHIMI , Kazuyuki WATANABE
CPC classification number: H04B15/00 , H03F3/193 , H04B1/0057 , H04B1/006 , H04B1/525
Abstract: A multiband transmission module includes a power amplifier and a multiband isolator. An output end of the power amplifier is connected to a single input terminal of the multiband isolator. The multiband isolator includes a low-frequency individual isolator and a high-frequency individual isolator. Input ends of the individual isolators are connected to the single input terminal of the multiband isolator. Output ends of the individual isolators are respectively connected to a low-frequency output terminal and a high-frequency output terminal of the multiband isolator.
Abstract translation: 多频带传输模块包括功率放大器和多频带隔离器。 功率放大器的输出端连接到多频带隔离器的单个输入端子。 多频隔离器包括一个低频单独隔离器和一个高频单独隔离器。 单个隔离器的输入端连接到多频段隔离器的单个输入端子。 各个隔离器的输出端分别连接到多频隔离器的低频输出端子和高频输出端子。
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公开(公告)号：US20240333231A1
公开(公告)日：2024-10-03
申请号：US18619743
申请日：2024-03-28
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Masatoshi HASE , Seiko NETSU , Shingo YANAGIHARA
CPC classification number: H03F1/3211 , H03F1/0288 , H03F3/245 , H03F3/602 , H03F2200/451
Abstract: A power amplifier circuit includes a distortion compensation amplifier circuit that includes a first amplifier that amplifies a first signal distributed from an input signal, and a second amplifier connected in parallel to the first amplifier, that amplifies a second signal distributed from the input signal and having a different phase from the first signal, and outputs an amplified signal obtained by combining a signal output from the first amplifier and the second amplifier, and an output amplifier circuit that outputs an output signal obtained by amplifying the amplified signal. The distortion compensation amplifier circuit further includes a control circuit that controls, based on power of the input signal, the first gain and the second gain to compensate for a change in a phase of the output amplifier circuit with respect to a change in the power of the signal input to the output amplifier circuit.
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Patent Agency Ranking
公开(公告)号：US20210336591A1
公开(公告)日：2021-10-28
申请号：US17237276
申请日：2021-04-22
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Shingo YANAGIHARA
Abstract: A multi-finger transistor includes unit transistors each including a first terminal electrically connected to a reference potential, a second terminal that receives an RF signal and a bias current, and a third terminal that outputs an amplified signal; a common input terminal electrically connected in parallel to the second terminals of the unit transistors and that receives the RF signal; a common bias terminal electrically connected in parallel to the second terminals of the unit transistors and that receives the bias current; a common output terminal electrically connected in parallel to the third terminals of the unit transistors and that outputs the amplified signal; and first resistance elements each of which is electrically connected between the common input terminal and the second terminal of a corresponding one of the unit transistors and each of which cuts a DC component of the bias current.
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公开(公告)号：US20210152139A1
公开(公告)日：2021-05-20
申请号：US17099297
申请日：2020-11-16
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Shingo YANAGIHARA , Satoshi TANAKA
Abstract: A power amplifier circuit includes an input-stage power amplifier configured to receive a radio-frequency input signal, an output-stage power amplifier configured to output an amplified radio-frequency output signal, and an intermediate-stage power amplifier disposed between the input-stage power amplifier and the output-stage power amplifier. The intermediate-stage power amplifier includes a first transistor, a second transistor, and a capacitor having a first end connected to an emitter of the first transistor and a second end connected to a collector of the second transistor. The intermediate-stage power amplifier receives a signal at a base of the second transistor thereof and outputs an amplified signal from a collector of the first transistor thereof.
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公开(公告)号：US20240039484A1
公开(公告)日：2024-02-01
申请号：US18361222
申请日：2023-07-28
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Shingo YANAGIHARA
CPC classification number: H03F1/52 , H03F3/211 , H03F2200/451
Abstract: A power amplifier includes an amplifier circuit configured to amplify a radio frequency input signal, a bias circuit configured to output a bias current to the amplifier circuit, and a bias suppression circuit configured to suppress the bias current based on the radio frequency input signal. The bias circuit includes a first transistor including a collector and a base that are electrically connected to a first node to be input with a current and an emitter electrically connected to a second node, a second transistor including a collector and a base that are electrically connected to the second node, and a third transistor including a base electrically connected to the first node and an emitter, the third transistor being configured to output a bias current from the emitter. The bias suppression circuit draws a current from the second node of the bias circuit based on the radio frequency input signal.
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公开(公告)号：US20210408982A1
公开(公告)日：2021-12-30
申请号：US17470115
申请日：2021-09-09
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Shingo YANAGIHARA
IPC: H03F3/21
Abstract: A power amplifier circuit includes a first power amplifier, a balun, a second power amplifier, and a third power amplifier. The second and third power amplifiers each include unit bipolar transistors each including a first terminal electrically connected to a reference potential, a second terminal, and a third terminal that outputs an amplified signal; a common input terminal electrically connected to the second terminals of the transistors and receives an RF signal; a common bias terminal electrically connected to the second terminals of the transistors and receives a bias current; a common output terminal electrically connected to the third terminals of the transistors and outputs the amplified signal; and resistance elements each of which is electrically connected between the common input terminal and the second terminal of a corresponding one of the transistors and cuts a DC component of the bias current.
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公开(公告)号：US20210013164A1
公开(公告)日：2021-01-14
申请号：US16925006
申请日：2020-07-09
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Tsutomu KOBORI , Hiroshi OKABE , Shigeru YOSHIDA , Shingo YANAGIHARA , Yoshifumi TAKAHASHI
IPC: H01L23/66 , H01L27/06 , H01L49/02 , H01L29/737
Abstract: A ground pad is disposed on a substrate. A plurality of transistors, each grounded at an emitter thereof, are in a first direction on a surface of the substrate. An input line connected to bases of the transistors is on the substrate. At least two shunt inductors are each connected at one end thereof to the input line and connected at the other end thereof to the ground pad. In the first direction, the two shunt inductors are on opposite sides of a center of a region where the transistors are arranged.
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