In a standard cell of a semiconductor integrated circuit device, a metal interconnect corresponding to an input node is connected to the gates of first and second transistors, and a metal interconnect corresponding to an output node is connected to the drains of third and fourth transistors. A metal interconnect corresponding to an intermediate node is connected to a gate interconnect corresponding to the gates of the third and fourth transistors through a gate contact. The gate contact is placed at a position overlapping the third transistor in planar view.