A semiconductor memory device includes a stacked body, a plurality of columnar bodies, a plurality of bit lines, a plurality of contacts, and a plurality of dividing portions. The plurality of dividing portions is located separately in the third direction, each extending in the first direction in the stacked body, and dividing one or more gate electrode layers including the lowermost layer of the plurality of gate electrode layers in the third direction, when the one side is the lower side. The plurality of columnar bodies includes five columnar bodies provided in a region between two adjacent dividing portions among the plurality of dividing portions. Regarding each columnar body provided in the five columnar bodies, a separate bit line provided in the plurality of bit lines is present between a bit line provided in the plurality of bit lines and electrically connected to the columnar body, and each bit line provided in the plurality of bit lines and electrically connected to a columnar body adjacent to that columnar body at the shortest interval among the five columnar bodies.