- 专利标题: Floating Voltage Suppression in High Speed Multiplexers
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申请号: US18182996申请日: 2023-03-13
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公开(公告)号: US20240313780A1公开(公告)日: 2024-09-19
- 发明人: Chieh-Yuan Chao , Jenghung Tsai
- 申请人: PARADE TECHNOLOGIES, LTD
- 申请人地址: US CA San Jose
- 专利权人: PARADE TECHNOLOGIES, LTD
- 当前专利权人: PARADE TECHNOLOGIES, LTD
- 当前专利权人地址: US CA San Jose
- 主分类号: H03K19/173
- IPC分类号: H03K19/173 ; H03K17/693 ; H03K19/003 ; H03K19/1776
摘要:
An electronic device includes two multiplexer branches, a modulation circuit, and an output interface coupled to the modulation circuit and two multiplexer branches. A first multiplexer branch generate s first output signal from a first selection signal, a first inverse signal, and a first input signal. The first inverse signal is substantially complementary to the first selection signal. A second multiplexer branch generates a second output signal from the first selection signal, the first inverse signal, and a second input signal. The modulation circuit generates a logic output signal from the first input signal and the second input signal, independently of the first selection signal and the first inverse signal. The output interface generates a multiplexed signal tracking one of the first input signal and the second input signal based on the first output signal, the second output signal, and the logic output signal.
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